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Cadence RTL Compiler supports Oki Soc design platform

Posted: 23 Dec 2004 ?? ?Print Version ?Bookmark and Share

Keywords:oki electric? uplat? soc design? rtl compiler?

Cadence Design Systems Inc. announced that Oki Electric Ind. Co. Ltd has taped out a chip for Oki's uPLAT SoC design platform with the new low-power capability of Cadence Encounter RTL Compiler synthesis. With Encounter RTL Compiler, Oki reduced power by 45 percent and area by 12 percent.

"At Oki, we are using Encounter RTL Compiler for our most important designs, based on our uPLAT System LSI Design Platform," said Shinji Furuno, a senior manager of silicon platform design department, LSI Design division at Oki. "Encounter RTL Compiler's global synthesis enabled us to substantially reduce power and area, while producing a netlist that sped us through place and route more cleanly than we had experienced with previous technologies," Furuno added.

The Encounter RTL compiler includes a set of global focus algorithms to maximize the performance of the most challenging low-power designs. It works with existing design flows to increase chip performance, decrease design times, and provide the highest QoS.

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