Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > FPGAs/PLDs

Memory interface package woes

Posted: 27 Dec 2004 ?? ?Print Version ?Bookmark and Share

Keywords:fpga? memory interface ic?

Previously, I have addressed the component packaging problems found in FPGAs and perhaps given the impression that other packages were OK.

However, after attending Memcon in Santa Clara in November, I learned that packaging defects and the resulting simultaneous switching noise (SSN) they cause extend to the area of memory interface ICs.

Memcon was composed of two camps from the memory industry: memory suppliers and memory interface suppliers. The former provide high-performance memory devices while the latter provide memory controllers. Of the two camps, the suppliers of high-performance memories have seen the light and have switched their packaging options from traditional TSOPs to BGAs. But, save one supplier, all the key providers of memory controllers, in the form of interface components or IP, appear not to be accounting for signal integrity issues in their package designs.

This became glaringly apparent in a panel session chaired by Rick Merritt of EE Times. The participants included the aforementioned primary memory interface suppliers. When these participants were questioned as to whom among them provide 3-D models of their packages to their customers, no hands were raised. The question was taken down a step to ask which suppliers provide 2-D models. Again, no hands.

The failure of these suppliers to address packaging issues is another critical oversight. These memory controllers interface to the parallel address and data buses that have rise and fall times that operate at an order of magnitude faster than they did even two or three years ago. This has moved memory interface packaging issues from the "don't need to care" to "have to care" space.

And, as with previous columns, how these problems affect the industry can be readily illustrated by a real-world design problem. One of my current clients is building a client/server product using a state-of-the-art microprocessor from one of the industry's leading suppliers. This client was experiencing noise problems that they were having difficulty tracing. It turns out that the problem is a result of SSN in the memory interface of the MPU.

So, again, it is incumbent on the industry as a whole to address these packaging problems. Otherwise, everyone will be singing the same, sad SSN song.

- Lee Ritchey

Speeding Edge

Lee Ritchey is the founder and president of Speeding Edge (, a leading industry training and consulting firm specializing in the high-speed PCB and system design disciplines.

Article Comments - Memory interface package woes
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top