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Synopsys ESP speeds verification of Metro platform memories

Posted: 27 Dec 2004 ?? ?Print Version ?Bookmark and Share

Keywords:artisan components? esp full-custom memory? verification?

Synopsys Inc. announced that Artisan Components Inc. has standardized its ESP full-custom memory equivalency checker for the latest low-power, high-density Metro Platform memories. ESP's symbolic simulation technology enabled Artisan to verify its memory generators, while realizing a 5X reduction in time-to-results as compared to verification methods that rely on traditional simulation only.

ESP is a fast, comprehensive memory equivalency checker that addresses the gap in full-custom verification by thoroughly and quickly comparing a Verilog simulation model directly against the corresponding HSPICE netlist.

"Artisan's standardization on ESP further validates our continued investment in a comprehensive range of industry-leading verification technologies that cover the RTL, gate and transistor-level space," said Bijan Kiani, VP of marketing at Synopsys. "ESP, coupled with our Formality equivalence checking software, delivers the industry's only functional equivalence checking solution capable of verifying complex SoCs that contain full-custom memories, cell-based logic, and third-party IP blocks," Kiani added.

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