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Embedded algorithms for co and parallel processing

Posted: 29 Dec 2004 ?? ?Print Version ?Bookmark and Share

Keywords:celoxica? embedded system level algorithmic? design tool? dk design suite? fpga?

We like to think of embedded systems as having to contain a microcontroller or microprocessor. It's true that the programmed nature of an embedded controller is a clear defining line. But, there are different approaches to the same problem. Sometimes those approaches are subtle and slight in difference. Other times, they are drastically different approaches.

Take for example, a micro performing DSP functions under software control. Source streams of data could be DMA'ed into an indexed scratchpad where it is operated upon and transported out. That's a pretty standard approach.

A slightly different approach is to use a dedicated DSP chip to directly handle system functions. Maybe a small dedicated microcontroller could be added for housekeeping and mundane functions. This is a slight variation on a theme and similar to the first approach.

But, instead of firmware based programmable micro's calling the shots, what if logic is spun to handle in hardware, the algorithms the software is trying to emulate? This is a different approach to an embedded system since there may not be a micro per se.

But, the key issue here is the idea that an algorithmic process can be captured and implemented at such a high level. That's what Celoxica is touting with its Embedded System Level Algorithmic architectural design tool.

The latest release of their DK Design Suite extends the functionality of this approach and speeds production grade FPGA designs and rapid asic and soc prototypes.

DK3.1 is an embedded system design tools for SoCs and FPGAs sourced from C-based Algorithms. From complex C algorithms (Handel C or System C), VHDL and Verilog output are generated. The result is RTL code which is compatible with common ASIC design flows. FPGA's are prime targets as well for this approach. Here, FPGA's act as a rapid prototype, test, and verify vehicle. They can be used for production as well.

DK3.1 uses optimized EDIF netlists to communicate with key high density and high performance FPGAs. The 3.1 version includes device support for Cyclone II and Stratix II from Altera Corp., and the Virtex-4 family from Xilinx Inc.

Celoxica also supports the Nexus-PDK co-verification system for evaluating and prototyping. This includes Platform Developers Kit (PDK) board and processor support packages.

A nice thing about Celoxica's design environment is that you can still mix and match algorithmically compiled functional blocks with embedded micros, peripherals, memory, and programmable logic. It really is more of a SoC design tool.

The ability to compile key algorithms into hardware can serve to optimize logic density, perform hardware acceleration, make independent stream processors, and create parallelism.

Version 3.1 of Celoxica's DK Design Suite is already available, with tight integration to FPGA vendor software such as Altera's Quartus II v4.1 and ISE 6.3i from Xilinx also available.

Delivered with DK3.1, Celoxica's upgraded PDK packages support Nios, Nios II and MicroBlaze soft-cores and all popular FPGA bus specifications including Avalon, FSL, OPB and PLB. Also available, the company's COTS boards integrate to DK3.1 to enable rapid implementation of SoC prototypes. A new set of parameterized IP including an FFT library and a Cordic Library is also available with the DK3.1 version.

- Jon Gabay

eeProductCenter




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