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SerDes core supports 155Mbps to 3.125Gbps

Posted: 29 Dec 2004 ?? ?Print Version ?Bookmark and Share

Keywords:system-on-a-chip? soc? lsi logic? hydra? serializer/deserializer core?

LSI Logic Corp. released its Hydra serializer/deserializer (SerDes) core that is a pre-verified physical layer interface, supporting a large menu of industry-standard interfaces that reduce the risk and turnaround time of product development for storage systems, networking and telecommunications applications.

"By leveraging our extensive experience in high speed SerDes technology, we're providing a highly flexible and configurable core that satisfies the requirements of a broad cross section of custom logic applications," said Jean Bou Farhat, VP for LSI Logic's CoreWare. "Both our ASIC and RapidChip Platform ASIC customers will benefit from having a single SerDes that supports applications ranging from 155Mbps Sonet traffic to 3.125Gbps XAUI and CX4 interfaces."

The company added that the new Hydra core can be easily integrated into a cell-based ASIC or into the RapidChip Xtreme family of slices. Operating at 100Mbps to 3.2Gbps with in-system selectable LVDS and PCML I/O options, it supports both 10bit parallel interfaces (10 bits or 20 bits wide) and 8bit parallel interfaces (8 bits or 16 bits wide). Additionally, for a given speed of operation, the core operates with a wide range of reference clock frequencies.

The core has full SerDes capability including clock and data recovery circuitry on the receiver to recover both clock and data from a received bit stream. Alternatively, the core may be configured to support source synchronous interfaces where a separate clock is sent with the data.

With this flexibility, the Hydra core supports a number of standards and data rates including, but not limited to Gigabit Ethernet, SGMII, XAUI, CX-4, Serial RIO, Parallel RIO, SFI4.1, SPI4.2, SPI5 and HyperTransport. The unique in-system selectable LVDS and PCML I/Os allow the design of single ports that support both LVDS-based and PCML-based interfaces such as SPI4.2 (LVDS) and XAUI (PCML), LSI Logic added.




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