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Convergence of EDA technologies: Key to silicon success

Posted: 03 Jan 2005 ?? ?Print Version ?Bookmark and Share

Keywords:market? outlook? business? growth? trend?

Ko: These days, everyone is exercising fiscal caution, and cost of results has never been more important.

The 2005 technical outlook for eda demands robust design, verification and design for manufacturing (DFM) solutions that produce quality silicon in a timely fashion at the lowest possible cost. Engineers who use such solutions will achieve silicon success in 2005 and beyond.

Technical challenges in 2005 will be driven primarily by consumer demand. In countries like China, for example, economic growth is fueling new markets as local consumers participate more in the global economy.

The global consumer market is especially notable because designers of portable systems must be sensitive to cost, power consumption and size. Those requirements necessitate smaller silicon processes, which in turn increase complexity. As we move to 90nm processes and beyond, gate counts will soar and manufacturing processes will become increasingly complex.

At Synopsys, we believe the best way to address these trends is to provide solutions that focus on convergence in four key areas: design, verification, IP reuse and DFM.

In design, engineers need solutions that address the complex and interrelated realms of area, timing, signal integrity, test and yield. Only a design platform that offers comprehensive technologies in all of these areas will meet the demands of today's designers.

On the verification front, engineers need a solution that converges on proven technology from the system level to the transistor level. The verification platform must be able to produce timely, low-risk results and still be able to handle multiple design languages for analog, digital and mixed-signal systems.

IP reuse is essential to meet ever-decreasing design cycles and tight time-to-market requirements. Engineers must have access to a broad portfolio of IP that is fully verified and silicon proven. That IP also must be reusable, so engineers can import blocks from previous designs, secure in the knowledge that it will fit seamlessly into the next generation of systems.

Lastly, there must be a convergence of all these domains with DFM. In deep submicron design, the historical separation of chip design from the realms of mask making and silicon manufacturing will no longer work. Unless engineers design chips with tools that incorporate knowledge of the mask making and silicon fabrication processes, needless costly iterations will occur. These iterations can lengthen time-to-market to such an extent that a project might miss its market opportunity altogether.

Engineers who use these technical solutions must also keep an eye on quality of results (QoR), time to results and cost of results. When we look at QoRs, we aren't merely concerned with the end product. We must expect QoR across every one of the aforementioned domains of area, timing, signal integrity, test and yield. Only if QoR is established in all of these areas will engineers get working silicon to market.

Time to results primarily hinges on quality. If a product has bugs, an inordinate amount of time is lost on redesign. After quality, time to results hinges on ease of use so that engineers spend time designing, not learning how to operate and integrate tools. EDA solutions must also work in concert across all areas of design, verification and DFM or precious time is lost. Finally, time to results demands a broad IP portfolio to relieve designers of the time-consuming task of locating reliable libraries.

These days, everyone is exercising fiscal caution and cost of results has never been more important. Costs are spread over the cost of design tools and the equipment that runs them, the cost of the engineers' time, and the cost of manufacturing the product. Only a broad portfolio of quality EDA technology that is convergent and efficient can help engineers control costs.

- Dr. Howard Ko
VP of Sales, Asia Pacific
Synopsys Inc.

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