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Aldec blends SystemC, HDL debugging

Posted: 04 Jan 2005 ?? ?Print Version ?Bookmark and Share

Keywords:asic? fpga? aldec? riviera 2004.12? systemc?

Expanding its capabilities for mixed-language simulation of ASICs and FPGAs, Aldec Corp. announced last week (Dec. 27) the release of Riviera 2004.12. New features include integrated SystemC and HDL debugging, assertion-based verification, and functional code coverage.

Riviera 2004.12 lets designers instantiate VHDL and Verilog models in SystemC code, promising coverage of all possible combinations of HDL and SystemC modules in the design hierarchy. Users can instantiate HDL in SystemC without the use of wrappers or PLI or VHPI overhead. The latest release also includes MinGW, an open-source package that includes a GCC compiler and a GDB debugger, allowing co-simulation with SystemC and HDLs.

A new assertion engine supports OpenVera assertions, Property Specification Language (PSL) and SystemVerilog assertions. Tutorials, samples, and template wizards are included.

Riviera 2004.12 also makes it possible to collect and visualize assertion data in a new functional code coverage viewer, along with HDL code. Assertion coverage views illustrate portions of the design's functionality that were or were not covered during verification.

Finally, system-independent libraries let design teams share compiled libraries across multiple platforms without having to recompile. Aldec's independent libraries support X86 for Windows and Linux, as well as Sparc for Sun Solaris. Riveira 2004.12 is available now starting at $12,450. A free evaluation copy is available online.

- Richard Goering

EE Times

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