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When bad packages kill good PCBs

Posted: 10 Jan 2005 ?? ?Print Version ?Bookmark and Share

Keywords:pcb? speeding edge? caspian networks? mahi networks? xilinx?

Best practices for avoiding design disasters

"Before you put a part on a board, build a test circuit. See if it in fact works the way it's claimed to work."

- Lee Ritchey, Speeding Edge

"Be very cautious, especially on FPGA packages, to try not to use all the pins and to not mix signals of different buses on the same quadrant of the package."

- John Zaszio, Caspian Networks

"Ask for reference customers. If they can't produce any, that might be a yellow flag."

- Ramon Hecker, Mahi Networks

"Work with your suppliers and get enough information. Don't make any assumptions."

- Nozad Karim, amkor

You don't have to go far to hear the horror stories: delayed products, expensive PCB respins, even companies forced out of business-all due to the failure of IC or FPGA packages to work once they're placed on a PCB. The issue has reached a crisis point for thousands of PCB designers.

At a technology level, the main problem is that parasitic package inductance is causing functional failures due to Vcc and ground bounce. Once that happens, the only recourse is a board redesign with a different part. But more galling to many PCB designers is the lack of documentation, models and support from device vendors around signal integrity issues.

"If we don't fix this, there are going to be lots of engineering projects that fail," said consultant Lee Ritchey, president of Speeding Edge.

Packaging problems are worst for off-the-shelf ICs and FPGAs, both of which must serve a wide range of possible applications. ASICs, custom-designed for one application only, tend to be less problematic. IBM Corp. and Intel Corp. stand out as ASIC and component providers that get it right, but they're the exception, not the rule, designers say.

FPGA and IC providers say they're aware of the problem, and are stepping up their efforts to build better packages, run 3-D electrical modeling and provide better information for customers. But they also note that the entire system, including chip and board, must be optimized for signal integrity, and note that they have no control over how customers design their boards.

Ramon Hecker, director of hardware engineering at optical-networking provider Mahi Networks Inc., is going through a nine-month schedule delay with re-engineering costs of $20 million due to an FPGA that didn't work as promised on a high-speed PCB.

Mahi was designing what Hecker describes as a "cutting-edge application" involving 3.125GHz backplane links. The design called for FPGAs with integrated serdes capability to be used as serial links. But test data showed severe ground bounce and power bounce on the board, as well as performance problems related to the operation of the serdes links in the system environment.

Thus began a four- or five-month process of trying to work things out with the FPGA vendor. It was hard to get the vendor to respond to or even acknowledge the test data, Hecker said. "They kept telling us other customers were not having a problem," he said. "We kept asking to speak to reference customers, but they told us none of them were willing to speak to us."

Hecker said the vendor provided a lot of "cookbook" data on using the part, but cited a lack of documentation and support around known issues or problems that had come up with it. Only after months of pressure, he said, did people in the vendor's serdes technology group admit there was a problem. In the end, Mahi switched to a different FPGA vendor and so far, Hecker said, it looks like the new part will work.

John Zaszio, hardware architect at fiber-optics router provider Caspian Networks, is also running into problems with FPGA packages. There's a big difference, he said, between packages from FPGA vendors and ASIC packages from IBM, which he described as well-designed with controlled-impedance transmission lines for every signal in the package.

Zaszio is designing a framer interface SPI 4.1 board running at 10Gbps, with a source-synchronous clock running at 200MHz. There's a bus running from an IBM ASIC to an FPGA. On an adjacent chip, the same exact bus is running out of the FPGA package to the IBM ASIC.

"The noise and clock jitter are 10 times worse on the signals coming out of the FPGA package," he said. To get the FPGA to work, Zaszio said he has to be extremely careful with pin assignments.

Zaszio cited several FPGA packaging problems. These include inductance on the power supply plane, poor assignment of power and ground pins going to the PCB and poor decoupling inside the package for high-speed current spikes. I/Os do not use controlled-impedance transmission lines, and unless power and ground are assigned with low-inductance connections, it's easy to end up with simultaneous switching noise and false signals, he said.

Documentation, he said, is poor "from every vendor except IBM, and even some things from IBM." Application notes typically offer really bad advice, such as advocating the use of decoupling capacitors, which turn into inductors above 100MHz, said Zaszio. And only IBM provides decent electrical models of packages, he said.

Design tools don't help much either, Zaszio went on, because most provide analysis after pc-board layout. "The approach I've used for many years is to do a worst-case analysis ahead of time, come up with rules and make sure there's sufficient power distribution, decoupling and signal transmission line characteristics so PCB designers don't get into trouble."

Consultant Ritchey hears the stories all the time. After raising the issue in a series of PCB Perspectives columns in EE Times, Ritchey says he's been flooded with calls and e-mails from board designers. "Almost every day, I get a call," he said. "I've got one on my desk right now where the design will have to be scrapped." Even worse, said Ritchey, is the client in Fremont, Calif., that went belly-up because of packaging problems-the whole company is gone.

"The worst part of it," said Ritchey, "is that when people call me and it's the problem I thought it was, I have to tell them they're dead. It's a rotten job."

The problem, he said, is excessive inductance in the power paths of IC packages. "When you drive transmission lines, very rapidly changing currents have to be drawn from the power supply through the package inductance. That gives rise to Vcc and ground bounce," said Ritchey.

Vcc bounce occurs when the Vcc terminal of the IC die switches from 0 to 1. Ground bounce occurs when the ground rail of the IC switches from 1 to 0. Both are forms of simultaneous switching noise, and both cause transient spikes and logic errors.

The problem first appeared in the early 1990s with TTL parts. It showed up later in quad flat packs and was temporarily fixed by going to ball grid arrays. But now, Ritchey observed, wide data buses and fast edge rates have brought the problem to BGAs. And it's not just FPGAs, but components of all kinds that cause problems.

According to Ritchey, the only two suppliers that get it right are IBM and Intel. And when it comes to documentation, these are the only two he termed "decent." Otherwise, there's a lack of documentation from component vendors and a dearth of good electrical-packaging models, he said.

"IC vendors have to do the 3-D modeling, but there's a serious lack of people with those skills," Ritchey said. "There are very good tools-the EDA vendors are doing their part. But it's like trying to run an airline that doesn't have any pilots."

Ritchey has his own horror story. When he was head of 3Com's signal integrity engineering in 1998, he had a board fail due to Vcc and ground bounce from a processor. When he asked the vendor if it built test circuits, the answer was no. When he asked how the vendor determined if the parts worked, the response was, "We give them to our customers and they tell us."

Semiconductor suppliers are addressing the problem, but doing so is far from simple. While ASICs are custom-designed for a specific application, FPGAs must cover a broad range of customers. Thus, by definition, the packaging is "somewhat compromised," said Tarun Varma, director of packaging at altera Corp. "We need to do a better job of defining the boundary conditions where the product may have performance compromises," Varma said. "For example, if a customer switches all 800 I/Os at the highest possible drive strength, that customer will have a problem."

Varma said Altera does both 2-D and 3-D modeling, checks inductance and signal integrity, and builds test circuits. It provides Ibis models to customers and will provide 3-D models on demand. "Going forward, we plan to give a lot more information on our package models, but the usage of package models has to be proliferated across the industry," he said.

Mark Alexander, product application engineer in Xilinx Inc.'s advanced-product group, observed that FPGAs with wide RAM interfaces and fast edge rates are among the most problematic. But it's not just the package, he emphasized. Alexander noted that the package power distribution system and the PCB power distribution system must be properly designed, so that noise does not exceed 10 percent of the nominal power supply voltage. This becomes more challenging as supply voltages decrease and current goes up.

Xilinx provides Ibis models and offers S-parameter and Spice models via a licensing program. But models are no panacea, noted Alexander. First, he said, models don't incorporate coupling to other signals on the package. Further, there is no standard package model format; 3-D models can be very complex and Xilinx has limited visibility into what kind of application the device will go into.

Some national semiconductor Corp. customers are running into simultaneous switching noise and ground bounce problems from networking ICs, mixed-signal components and RF devices, said Sada Patil, VP of advanced-packaging technology at National. "It's a three-pronged issue-silicon, package and the board," he said. "At the end of the day you have to make it a cost-effective solution."

Patil said that National runs 3-D electrical models, builds some test boards and generally provides Ibis models to customers. In some cases, National provides 3-D models as well. The company is also working with its customers on package requirements, he said.

Texas Instruments Inc. is seeing parasitic package inductance in some of its ASICs and DSPs, said Mario Bolanos, director of semiconductor-packaging development. "We have seen a major increase in the amount of 3-D electrical models that we have to support," he said. "We have had some issues with Spice simulation coming out of these tools, but we are working those issues." Bolanos said TI formats the packaging information into a Spice circuit file and passes it to chip designers, the company's primary customers. "Packaging does not usually deal directly with the end customer," he said.

Amkor Technology, too, sees problems with parasitic package inductance "all the time," said Nozad Karim, director of characterization engineering at Amkor, one of the world's largest IC-packaging and assembly providers. But the package itself may not be the problem, he said. "Sometimes the package behaves well in isolation, but putting the package close to connectors or cables adds noise to the package. It's not because of the package, it's a system issue."

Board designers, he said, should work with silicon-packaging engineers to collectively optimize the system. To meet this need, Amkor is now offering design services to both IC and PCB designers.

What's most important, said consultant Ritchey, is that component providers realize packaging is crucial and provide good information. Failing to do so can prove catastrophic.

- Richard Goering

EE Times





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