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Agere serdes core rolls for 90nm ASICs

Posted: 07 Jan 2005 ?? ?Print Version ?Bookmark and Share

Keywords:agere systems? serdes core? 90nm? asic? serializer/deserializer?

Agere Systems Inc. is offering a serdes core for 90nm ASIC processes that's appropriate for several serial-interface standards. The 6.25Gbps serializer/deserializer can be used in serial ata, serial attached scsi, Fiber Channel, Gigabit Ethernet and PCI Express designs. Agere claims both the core size and power dissipation are half those of serial-interface cores.

To adjust for Fiber Channel's larger voltage requirements, transmit voltages in the core are programmable at the register level, said Greg Sheets, director for high-speed interface development. The serdes implements a primarily digital architecture with adaptive equalization that supports both nonreturn-to-zero and pulse-amplitude modulation.

The core supports multiple loop-back modes, including serial and parallel loop-back and a special high-speed buffer loop-back, the company said. An analog test bus integrated into the core allows power measurements at the serdes interface. Agere provides a special software tool, Eye Margin, for measuring eye closure at clock and data recovery level.

- Loring Wirbel

EE Times




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