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China to invest more in 0.18?m technology

Posted: 06 Jan 2005 ?? ?Print Version ?Bookmark and Share

Keywords:market? outlook? business? growth? trend?

Fujimura: Chinese fabs have a unique opportunity to invest more in 0.18?m technology, leveraging with the best eda technologies that are now available.

The semiconductor world continues to present exciting opportunities in 2005, particularly in Asia. consumer and wireless segments will drive cost and power, while the North American market will drive performance. The opportunities are significantly different though, depending on the type of business. In the mass market, the opportunity is to maximize the cost advantage as the mainstream semiconductor process technology migrates from 0.25?m to 0.18?m, while preparing for the 0.13?m node. However the opportunity in the leading-edge market is to be faster than the competition in ramping up the yield curve and combating the leakage current issues that are prevalent with 90nm generation ICs, and of even greater concern at 65nm.

Business opportunity for the mass market is to maximally leverage the 0.18?m technology node. Any EDA technology that helps reduce manufacturing costs will be key. While the rest of the world's semiconductor R&D resources are focused on the leading-edge nodes, Chinese fabs have a unique opportunity to invest more in 0.18?m technology, leveraging the best EDA technologies that are now available. Also, there are significant opportunities to deliver a higher rate of first silicon success by properly checking the design prior to tapeout for signal integrity, voltage drop and the effects of voltage drop on timing. An investment in design flows and methodologies that can reliably produce first silicon success will pay off handsomely. Another opportunity is in mask cost reduction, for example by leveraging mask composition technologies. LCD design is a fast-growing segment that is enabled by the availability of complete and integrated EDA solutions running on affordable 64bit Linux systems.

At 90nm and below, the issues are significant, and therefore the opportunities great. The set of issues surrounding design for manufacturing (DFM) and related yield enhancement challenges give IDMs a chance to bring up yield faster than the foundries and their customers can do together. IDMs may do this through restrictive design methodologies that avoid manufacturing issues while the fabs ramp to handle the more general cases. Foundries will counter by continuing to drive for deeper relationships with the design community.

Co-investment also provides numerous opportunities, such as an extension of the common open-source database that can carry design information through the manufacturing steps. Openness and collaboration are key for successfully navigating the DFM reality. Baseline capabilities, such as OPC and silicon simulation, continue to advance. These technologies manipulate the mask data after the design is complete. The current trend is to create EDA technology and design methodologies that optimize for yield earlier in the process, i.e., during the design steps. These DFM enabled design flows help designers to visualize how their layout will look on silicon prior to mask manufacturer. By providing analog and custom designers with this feedback before tapeout, manufacturing factors can be considered during the design steps. Digital design systems can now automatically optimize for yield, simultaneously with area, performance and power during synthesis, placement, routing and in post-layout optimization. Technology is available to automatically trace back from failed test vectors a list of high probability causes for failure in the physical design. This is another example of linking design and manufacturing worlds through automation.

Leakage current is another huge issue at 90nm. At these feature sizes, an automated and proven low-power design flow integrated throughout the design steps is essential. One example: the automatic insertion of level shifter cells is an absolute must to avoid error-prone manual processes. Furthermore, the need for voltage islands or multiple voltage sources demands current-source-based timing models, a significant departure from the linear models being used today. Multiple threshold voltages, clock gating, power gating, back biasing and a whole host of techniques enable more power-efficient physical implementations. Power estimation throughout the design phases, starting with systems design, will provide the necessary feedback.

System-in-package (SiP) is also an emerging trend that plays to the strengths of the Asia region. SiP complements SoC in the ever-increasing need for increased complexity in minimum form factor. EDA systems are now available to co-design chips, packages and boards efficiently. This enables electronic systems to implement in a single package a function that combines RF, analog, flash and digital functionality without requiring a process that can economically accommodate an all in one SoC substrate.

It is eminently clear that no one company, or even an entire industry, can tackle these challenges alone. The entire design chain must collaborate to enable semiconductor designs that are simultaneously small, fast and reliable, while providing a long battery life and immediate high yield on first tapeout. To deliver this while meeting the ever-increasing time-to-market pressures is where the battle will be fought.

- Aki Fujimura
CTO, New Business Incubation
Cadence Design System Inc.




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