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Ceva uses Synopsys Galaxy, Discovery for DSP, interface chips

Posted: 13 Jan 2005 ?? ?Print Version ?Bookmark and Share

Keywords:ceva-teak dsp? interface chips? galaxy? discovery?

Ceva Inc. has taped out its next-generation high-speed serial interface chips and the CEVA-Teak DSP using Synopsys Inc. Galaxy and Discovery platforms.

The CEVA design team cited Synopsys' convergent flow consisting of the following toolset as the reason for their success: Physical Compiler and Astro products for increased capacity, PrimeTime SI tool for signal integrity, Power Compiler products for power management, and VCS and NanoSim software for mixed-signal chip sign-off. The correlation of these tools was key to implementing their complex mixed-signal designs.

"We relied on Synopsys' routing and placement solutions for our 130nm chips, with an eye toward future designs of 3Gbps serial interfaces that we expect to develop in a 90nm process," said John Ryan, VP of communications and navigation at CEVA.

Antun Domic, SVP, general manager, implementation group at Synopsys, added, "CEVA relied on our design and verification solutions, especially the Physical Compiler and Astro tools, to bring their designs to tapeout. It was gratifying to see that our flows were able to give CEVA engineers the solutions they needed to complete their designs."

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