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High-voltage I/O module bolsters VXI digital tester

Posted: 14 Jan 2005 ?? ?Print Version ?Bookmark and Share

Keywords:interface technology? sr5031? i/o module? sr5000? digital test subsystem?

Test-and-measurement company Interface Technology announced the availability of its Model SR5031 high voltage programmable I/O module for the company's previously introduced SR5000 digital test subsystem. With the new vxi-compatible SR5031, the SR5000 (recognized by some as the highest performance digital test subsystem in the VXI world) adds to its list of capabilities.

Leveraging a scalable architecture
Leveraging the scalable architecture of the forerunner SR5000 system (which comprises a timing and control module and fixed logic (TTL, CMOS, differential ECL, etc) I/O modules, the SR5031 complements the SR5000 by providing programmable output levels and programmable input thresholds in the range of -12V to 12V, with a full 24V output swing. What's more, no external power supplies or high-powered chassis are required. Software drivers support labview" target=_blank>national instruments LabView and LabWindows/CVI.

Voltage parameters are programmed in groups of four pins, which results in up to four distinct I/O logic levels for each SR5031. Providing an overall pin-count of 32 (16 output pins and 16 input pins) per module, and 320 pins per system, the SR5031 lets ATE suppliers upgrade the digital capabilities of legacy test systems.

Dedicated memory
The SR5031 module also contains seven separate memory banks, each of 64,000 vectors in depth. These are used for generating stimulus patterns, expected response patterns, and recording UUT (unit under test) response data.

For their parts, the stimulus memories contain output, algorithmic and three-state patterns. These are used to define the stimulus output to the UUT. The Response Memories contain Expect, Algorithmic and Mask Patterns used to define an expected response from the UUT.

Record memory is used to store either the UUT response data, or the result of a comparison between the UUT response data and the Expect pattern. It's operated independently in a manner much like a logic analyzer. A sixteen-level state machine and nine system-wide digital comparators are used to control what data is saved in the memory. In addition to the record memory, each input channel is provided with a 16bit CCITT CRC (cyclical redundancy check) register for signature analysis applications.

Timing and voltage control
Each I/O module also contains ten separate timing generators for stimulus and response edge placement. Output pins can select from four timing generators to define the leading and trailing edges of each stimulus pin. Groups of eight output pins share an independent set of four timing generators for a total of eight stimulus timing generators per card.

Response pins can select from two response timing generators to define sample and compare edges, or the two response timing generators can be combined together for window-compare with glitch detection.

Output high and low voltages, and input logic threshold voltages, are independently user-programmable in groups of four channels. The output slew rate is internally controlled according to the output level.

Notably, the SR5031 provides the same capabilities already found in the SR5000 system, namely 50MHz data rates, RAM-backed and algorithmic pattern generation, and per-pin data formatting (in NRZ, RZ, RONE, RTC and RI formats). It also provides the SR5000's multi-level triggering and logic analysis, with 100ps delay and pulse width resolution. Finally, the SR5031 also supports Realtime Compare, with the 64,000 test vectors.

Guided probing
The SR5000 itself provides high-speed digital pattern generation, response comparison, logic analysis, and guided probe and fault diagnostic capability. In particular, a GPM (SR5000GP Guided Probe Module) provides the capability to read test points (nodes) on a UUT (unit under test) to determine Pass/Fail conditions.

The GPM also adds more clocks, triggers, and sync to the SR5000 subsystem. The guided probe is capable of testing and detecting high, low, and indeterminate states. It can also detect pulses and measure analog voltages. Upon determination of the Pass/Fail state, the guided probe stores the UUT response along with the compare results.

The probe uses an active input to reduce circuit loading and serves to condition the UUT signal before routing it to the guided probe logic in the GPM. An activation switch is located on the probe body to trigger or continue test execution. The SR5000GP Guided Probe Module is supplied as a separate, single-slot, C-size VXI Guided Probe Module.

- Alex Mendelsohn

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