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TSMC validates 90nm process using Mentor Graphics Calibre xRC

Posted: 14 Jan 2005 ?? ?Print Version ?Bookmark and Share

Keywords:calibre xrc? 90nm? test chip? extraction tool?

Mentor Graphics Corp. disclosed that Taiwan Semiconductor Corp. (TSMC) used a comparison of Calibre xRC results, field solver data and silicon measurements as part of the validation for its 90nm process technology. According to Edward Wan, senior director of design service product marketing at TSMC, the objective of the TSMC 90nm test chip program was to validate the stability of extraction correlation of the 90nm process using third-party vendor extraction tools such as Mentor Graphics Calibre xRC.

The TSMC 90nm test chip program showed that the Calibre xRC results matched measured silicon as well as industry-standard numerical tools for parasitic resistance, inductance and capacitance (R, L and C). TSMC and Mentor Graphics worked collaboratively on the test structures and the measurement technique to accurately quantify and measure 90nm parasitic effects. The test structures that were developed comprised a wide range of line widths and pattern densities to evaluate the effects of process variation across the wafer and across a single die.

The Calibre xRC tool can also support key 90nm process capabilities including selective process biasing, length of diffusion (LOD), source/drain and polysilicon gate resistance and metal fill. In modeling such advanced silicon processes the Calibre xRC tool extracts highly accurate RLC parasitics to enable a complete array of analysis requirements.

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