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Silterra adopts HPL IP to speed 0.13?m CMOS process

Posted: 19 Jan 2005 ?? ?Print Version ?Bookmark and Share

Keywords:hpl technologies? cmos process? tdsram? techxpress? sram?

Silterra Malaysia Sdn. Bhd and HPL Technologies Inc. revealed that their collaborative work has been instrumental in reducing the development and debug time for Silterra's new 0.13?m CMOS process technology. Exercising Silterra's proprietary bitcell in HPL's TechXpress TDSRAM, Silterra was able to shorten its test vehicle development cycle time down to mere weeks and debug its initial 0.13?m CMOS process, speeding its success of achieving functional 4Mb and 8Mb SRAMs.

As part of the collaboration, Silterra licensed HPL's TechXpress IP, which was customized to Silterra's design rules and proprietary bitcells. HPL's Dallas-based test lab also provided test services and assisted Silterra in analyzing and debugging initial wafers in the new process, using the unique programmed yield signatures available in the TDSRAM.

The TechXpress TDSRAM is part of HPL's family of array-based IP test chips for technology development, characterization and manufacturing monitoring.

Silterra plans to offer its 0.13?m design kit in the second quarter and start pilot production in the third quarter of this year.





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