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Startup claims to optimize IC layouts for yield

Posted: 21 Jan 2005 ?? ?Print Version ?Bookmark and Share

Keywords:ic? nannor technologies? router? acuma?

Even the best chip layouts need some help to maximize IC yields, according to startup Nannor Technologies Inc., which is quietly preparing a layout optimization tool.

Calypto was launched in late 2002 by Devadas Varma, CEO, and four co-founders. In the late 1990's, Varma was CTO of synthesis provider Ambit Design Systems. Following Cadence Design Systems' purchase of Ambit, Varma became a Cadence fellow until he left in 1999 to become a venture capitalist.

Calypto has thus far raised $22 million in venture capital, and has 42 employees. Initial funding came from Tallwood Venture Capital in 2002. Calypto is in beta sites with its first product and expects a formal product introduction in Q2 of 2005.

"Our mission is to enable the movement to higher levels of abstraction," Varma said. "It's primarily brought on by verification needs, as well as the need to factor in power as a constraint or goal."

Calypto's sequential equivalency checker promises to ensure that higher-level models are functionally equivalent to their RTL implementations. It could be used by verification engineers who want to compare SystemC models to RTL code, or design engineers who need to experiment with clocking, pipelines or resource sharing in order to meet power

constraints.

"It's an interesting technology," said Gary Smith, chief EDA analyst at Gartner Dataquest. "If it works as advertised it's going to be a major functional verification technology."

Meanwhile, Calypto is announcing the addition of two EDA veterans to its management team. Michael Sanie, who formerly oversaw the OpenAccess effort at Cadence Design Systems, is Calypto's new vice president of marketing and business development. Larry Lapides, former vice president of worldwide sales at Verisity Inc., is Calypto's new vice president of sales.

- Richard Goering

EE Times





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