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Altera bares industry's 'compelling structured ASIC solution'

Posted: 25 Jan 2005 ?? ?Print Version ?Bookmark and Share

Keywords:hardcopy ii structured asic? fpga? hardcopy ii? altera?

Designing ASICs require expensive tools that result in high-development costs and significant risk in bringing products to market in a timely manner. The latest HardCopy II structured ASIC from Altera Corp. responds to this turmoil in the ASIC market. Developed as an alternative to the standard cell, HardCopy II is a non-reprogrammable device seamlessly migrated from a Stratix II FPGA prototype.

Louie Leung, the company's marketing director for Asia, said, "HardCopy II was built on the success of Altera's first two generations of structured ASICs, the 0.18?m HardCopy APEX devices, and 0.13?m HardCopy Stratix devices."

HardCopy II structured ASICs are based on fine-grained architecture made up of transistor cells called HCells designed to support a seamless FPGA migration while providing the density, cost, performance, and power benefits of ASIC technology. HardCopy II was built-on a 1.2V, 90nm, 8-layer-metal, all-layer-copper process technology from TSMC.

The product delivers over 350MHz systems performance at 10 percent the cost and less than half the power consumption of the FPGA prototype. The ASIC family includes five members with logic densities up to 2.2 million usable gates, 8.7Mb of embedded RAM, 951 I/O, 384 18x18 multipliers, and 12 phase-locked loops (PLLs).


HardCopy II structured ASICs are available in densities ranging between one million and 2.2 million usable gates, with 0.8Mb to 9Mb of embedded RAM and 1.4 million ASIC gates to implement DSP functionality. Design engineers will be able to prototype and test their designs in the EP2S30, EP2S60, EP2S90, EP2S130, and EP2S180 members of the Stratix II FPGA family.

The HardCopy II structured ASIC family contains interface circuitry to meet the performance requirements of the latest SRAM and DRAM devices, including SDRAM, DDR SDRAM, DDR2 SDRAM, RLDRAM II, QDRII SRAM, and ZBT SRAM. External memory devices can be easily connected to HardCopy II structured ASICs to provide additional storage capacity outside of the on-chip memory resources without causing performance bottlenecks.

All HardCopy II structured ASICs are available in the industrial temperature range with junction temperatures ranging from -40deg;C to 100deg;C, and presented in lead-free packages.

Design migration
Depending on the constraining resource, different Stratix II devices can be used to prototype a HardCopy II design. Since Stratix II FPGAs support vertical migration, a number of pin-compatible prototype options exist. The HardCopy II device resource guide in Quartus II version 4.2 design software advises the designer as to the most efficient prototype FPGA to choose.

The HardCopy II device resource guide is generated every time a user compiles a Stratix II design using Quartus II software version 4.2 or later. The report can guide the user as to which HardCopy II structured ASIC will be suitable for their design.

Base arrays for all HardCopy structured ASICs are embedded with testability circuits. HardCopy II structured ASICs come standard with built-in self test (BIST) circuits for memory, PLLs, and boundary scan logic for the design. Altera's HardCopy II structured ASICs do not require any functional vectors from customers. Using automatic test pattern generation (ATPG) vectors, HardCopy II structured ASICs are tested on the structural design, resulting in very high test coverage of greater than 95 percent.


Designers can immediately begin prototyping their HardCopy II designs on a Stratix II FPGA using Quartus II version 4.2 design software. Customer prototypes of the first HardCopy II device will be available in the third quarter of this year. Volume pricing at 100,000 units starts at $15, with NREs starting at $225,000 for a full turnkey migration, including delivery of fully tested prototypes.

Additional licensing fees may apply for AMPP (Altera Megafunction Partners Program) partner IP. Quartus II software versions 4.2 and later support prototyping HardCopy II designs; future versions of the Quartus II software will provide HardCopy II timing and power estimations and will generate database files to be transferred to the HardCopy design center for migration.

As soon as all the required design guidelines are met and Altera accepts the design, the design can be migrated to a HardCopy series structured ASIC in two to four weeks. After the customer has approved the timing results, HardCopy prototypes will be available within five to seven weeks. Production units will be delivered within eight weeks from when the designer reviewed and approved the prototypes.

- Kathryn S. Gerardino
Electronic Engineering Times-Asia

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