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Platform enables designers to anticipate power requirements at start of design cycle

Posted: 25 Jan 2005 ?? ?Print Version ?Bookmark and Share

Keywords:faraday? powerslash? ip family? design platform?

Among the challenges to the low power design, Faraday said, the toughest one is that the designers have little control over the whole factors affecting power consumption until the end of the design. By then, the company added, it would be too late to make any effective adjustments.

To address this problem, Faraday introduced its PowerSlash IP family and design platform that enables designers to anticipate low power design requirements at the beginning of the design cycle that adopts a sequential design methodology from the transistor level, IP level, circuit level and up to the system level.

This new low power dissipation platform solution is comprised of a comprehensive IP portfolio, including standard cell library, memory (one port, two port, register file and ROM), IO (generic IO and special IO), and analog IPs (PLL, power on reset, voltage detector, oscillator, regulator, USB 1.1, USB 2.0, etc.). All of them are suitable for developing handheld SoCs. Additionally, the company provides a complete low power dissipation design flow from transistor to system level, including low power process technology, multi-Vt design flow/methodology, substrate biasing, multiple sleep modes, clock gating, power gating, voltage scaling, frequency scaling, multi-voltage island and system power management.

"In this progressive SoC era, one must take into consideration the low power requirements in every step of the IC design; anything less would only yield a disastrous result," commented Hsin Wang, R&D Associate VP at Faraday. "Additionally, a platform solution provider must be able to enhance its customers' uniqueness by fine-tuning their initial specifications."

The PowerSlash low power IP family and design platform will be ready in Q2 2005 using UMC's 0.18?m and 0.13?m process technology.

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