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Toshiba obtains power-efficient design using Synopsys Galaxy

Posted: 26 Jan 2005 ?? ?Print Version ?Bookmark and Share

Keywords:embedded processor? 90nm? soc? mobile applications?

Toshiba Corp. has achieved a 40 percent power reduction on its latest 90nm media embedded processor (MeP) system-on-chip (SoC) design using the Synopsys Inc. Galaxy design platform. The Galaxy platform's multi-voltage flow enabled Toshiba to realize an innovative power management architecture that balances power performance at the module level, making it well suited for mobile applications.

Takashi Yoshimori, technology executive SoC design, Toshiba Semiconductor Co., stated, "We implemented this architecture using the Galaxy platform's multi-voltage flow on our SoCs for mobile application design and achieved a 40 percent power savings for the module in which the technology is applied. We are now in the process of testing this Galaxy-based flow as a standard part of our low power design methodology."

Synopsys Galaxy design platform offers a solution for power management and power integrity. It delivers power optimization with support for clock-gating, multi-voltage designs, multi-threshold leakage, state retention power gating and power network synthesis.

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