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Toshiba, Celoxica boost C-based SoC design

Posted: 31 Jan 2005 ?? ?Print Version ?Bookmark and Share

Keywords:celoxica? soc? media embedded processor? fpga? dk design suite?

Combining electronic system level (ESL) design with a platform-based system-on-chip (SoC) solution, Toshiba Corp. and Celoxica Ltd announced Thursday (Jan. 27) a design flow for Toshiba's Media Embedded Processor (MeP) platform based on Celoxica's DK Design Suite of C-based synthesis tools.

The deal makes Celoxica's C-based design entry, simulation, co-simulation and synthesis software, as well as FPGA-based development hardware, available through an MeP RapidPlatform developer's kit. The companies will also engage in marketing and promotion in key market segments.

The MeP platform includes a processor, peripherals, and a programmable logic array. With the Celoxica deal, said Jeff Jussel, Celoxica's general manager for North America, MeP designers can compile C language algorithms for either the MeP processor or for a custom co-processor implemented in the on-board reconfigurable array logic.

"This announcement is the first of its kind, and it shows how system-level design will combine with SoC platforms to begin the next era of semiconductor design," Jussel said.

To allow simulations to include both library-based and custom intellectual property (IP), Toshiba and Celoxica have developed a co-simulation framework that unites Celoxica's DK simulator with Toshiba's MeP instruction-set simulator (ISS) and RTL simulator. Hardware implementation code generated by the DK Design Suite is directly equivalent to source simulation models.

In addition to design software and a development board, the MeP RapidPlatform kit also comes with a pre-configured, pre-loaded Toshiba MeP core. TFT touch screen and multimedia I/O is provided, along with support libraries for peripherals, MeP core instantiation, and MeP-to-hardware communication. Further details are available from Celoxica.

- Richard Goering

EE Times

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