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Cadence tool aims to tackle parasitics in RF design flow

Posted: 01 Feb 2005 ?? ?Print Version ?Bookmark and Share

Keywords:cadence design systems? wireless design problem? virtuoso platform? RF design flow?

Aiming to rid parasitic effects from RF design flow, the Virtuoso platform launched by Cadence Design Systems Inc. promises fewer re-spins and faster time-to-market with more efficient verification tool for 802.11b wireless LAN designs.

Aside from the RF IC flow and IC-to-system flow, the Virtuoso platform employs the EDA firm's design-engineering services, silicon-proven IP and Assura RF, its new RF extraction technology. The company has also teamed up with technology partnersCoWare, MathWorks, Helic and Agilentto provide a "complete solution."

"The solution helps manage or compensate the detrimental parasitic effects so as to facilitate better verification of the design before customers go to fab," said Kelley Perey, VP of Marketing for Cadence Virtuoso custom design platform.

RF problem
According to the market research firm International Business Strategies, parasitics is the main cause of wireless design failures. Perey agrees, calling parasitics one of the most crucial challenges in wireless design. "Since RF demands high-precision and silicon accuracy, parasitic effectssubstrate noise, substrate coupling and skin effectsare critical in RF circuits," she said.

RF extraction tools are important aides in any wireless design process as they help extract information on the parasitic effects in a design. "Since all these things [parasitics effects] may happen, you have to be able to predict what's going to happen and what those parasitics will do," Perey added.

After parasitics, the next problem is verification. "The second big challenge is verifying the three blocks (multimode MAC, multimode baseband processor and dual-band transceiver) individually, in an IC, and their operation in the context of the system," said Perey.

RF IC, System/IC flows
Based on 802.11b wireless LAN design IP, the two new design flows included in the Cadence offering focus on front-to-back RF and analog/mixed signal design, which at the same time bridging the gap between IC implementation and the entire system design. According to the company, these flows enable simultaneous verification of the RF, analog and digital domains together and verification of the wireless IC design in context of the system.

Business Communications Company Inc. reports that the worldwide wireless infrastructure expenditure is currently pegged at $177.5 billion and is expected to grow at an AAGR (average annual growth rate) of 2.5 percent to reach $201.2 billion by 2009.

Perey sees a huge opportunity in the wireless silicon arena. "In addition to the big companies, we see a lot of startups in the wireless business. In the United States, a lot of new venture funding in semiconductors is going to companies that are doing wireless or RF," she said.

- Margarette Teodosio
Electronic Engineering Times-Asia

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