Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > RF/Microwave

Architecture options for convergent devices

Posted: 01 Feb 2005 ?? ?Print Version ?Bookmark and Share

Keywords:rf? wireless? bluetooth? uwb? wi-fi?

The wireless phone is transforming into a device with 24/7 connectivity and support for a broad range of integrated, networked applications that will be coupled with private secure storage and always-on Internet service. Interacting with these applications will be an array of expandable I/O options, including Bluetooth-enabled headphones and displays, high-resolution flat-panel monitors, streaming data over UWB and natural language processing. Network connectivity will be maintained seamlessly even while roaming among networks such as Wi-Fi, WiMax and 3G/B3G (beyond 3G).

But integrating such diverse features into a form factor that can fit into a wristwatch requires significant and complex reuse of silicon. While the traditional approaches of ASIC intellectual property integration struggle to meet the rising cost and size challenges, various technological and architectural revolutions show promise for enabling the development of these tiny, low-cost and highly integrated consumer devices.

While the list of potential applications for convergent devices is large, in practice few must be supported at any one time since the activities the end user can simultaneously be occupied with is limited. For example, streaming an MPEG-4 movie co-terminal while composing a text message using speech-to-text is unlikely. Valid user scenarios need to be projected and clarified to minimize mandated performance levels and assess "reuse" targets for the underlying platform.

As for RF protocols, virtually every market region is fragmented by multiple and competing protocol standards. Complicating this landscape is the emergence of wireless local- and personal-area network (WLAN and WPAN) technologies that multiply the number of radio interfaces a universal device will need to support. Add the seemingly endless evolution of standards, and a daunting task emerges for OEMs and operators as they try to identify the critical network interfaces and bundle those combinations in an intelligent and consumer-friendly manner.

Today's mobile-device platform providers implement their solutions in custom ASIC hardware. The ASICs support baseband processing as well as applications. Chip-rate, symbol-rate and bit-rate co-processors are implemented as dedicated IP blocks and coordinated by programmable DSPs. The DSP is mated with a RISC processor and together they tackle the remaining real-time tasks, control and user-interface applications.

With this methodology in even a single-protocol device, it is typical to require multichip redesigns to reach qualification status for the platform. Future platforms that include multiple protocols on a single chip will face a daunting challenge to reach qualification status on multiple networks while still meeting their die-size goals.

Single vs. multiple protocols

As newer protocols emerge and new applications reach critical mass, the dominant mobile IC suppliers respond by aggregating more hardware IP with an ASIC methodology to create chips that cover more segments of the market. The OEM customers using these chips have little innovative latitude to create features, and as a result, devices based on these IC platforms will be difficult to differentiate. Without another approach, there will be a spiraling concentration of value in few firms, severely limiting any real innovation.

What the market needs is an underlying silicon platform that allows the OEM to take a more active role in defining the device features. To tackle this problem, several progressive approaches can be taken, each with advantages and disadvantages: reconfigurable logic processors, heterogeneous processor arrays, configurable heterogeneous processor arrays and high-performance DSPs.

Choosing the architecture

Reconfigurable logic processors give the system designer excellent levels of silicon reuse. Through technology innovation in FPGA architectures, power consumption has been squeezed; large gate counts are attainable on a single chip; and customized architectural blocks, such as multiply-accumulate (MAC) functions, are available. From a development standpoint, the hardware designer is familiar with the tool flow. But the power associated with reconfiguration and the inability to reconfigure on-the-fly precludes this technology from being used in the handset market.

A heterogeneous multiprocessor architecture, breaks processing into small software blocks running on multiple processorseach optimized for a different job. This type of design can achieve a high degree of silicon reuse. But the tool flow is made more complex by the introduction of multiple, nonstandard compute platforms as well as the nonstandard mix of compilation and debug tools. Communication protocols will place heavy computational demands on such a platform that exceed the maximum performance typically available. Even if a mix of processor types is included to support communications, traditional applications will suffer from the reduced flexibility.

A reconfigurable heterogeneous multiprocessor allows each processor element to be reconfigured, resolving the limitation on flexibility. The development flow now includes a combination of nonstandard hardware layout plus software development and debug on nonstandard architectures. But reconfigurability is not available on-the-fly and requires a power budget beyond what is acceptable in handheld devices.

The fourth approach is the high-performance DSP. The strength of this solution is the ability to implement the entire system in high-level language with the greatest opportunity for leverage and reuse. Since most communication protocols and applications can be described in the C language early in the system design process, this offers a great time-to-market advantage. From a development perspective, the environment is familiar, ubiquitous and imposes no learning curve on development teams. What will be challenging is finding a DSP with an ISA and overall implementation that are suitable for very-high-performance tasks.

Such an implementation would need to be invented from the ground up with communications processing in mind. The overall architecture, microarchitecture, logic design and transistor layout must work in concert to provide a high-performance, low-power ISA. Multithreading could provide significant value to communications-centric applications. Such software tasks could easily be broken into multiple simultaneously operating threads, further improving efficiency and power.

From a development perspective, all priority should be given to providing the software developer with the greatest possible productivity through efficient compilation and debug tools. Finally, the developer should be able to use a familiar APIssuch as Posix "pthreads"in which to implement the final code.

The introduction of such a DSP architecture would enable convergent devices to be delivered to consumers. Such a platform could directly benefit OEMs by helping them create high-value solutions with feature sets that could much more easily be kept "secret" from their competition. OEMs could also leverage the multiprotocol flexibility to introduce models into multiple regions much more quickly and achieve higher volumes on their core platform hardware. The flexibility of such platforms would give greater freedom to developers and result in smarter and more innovative products that would invigorate and transform the market for handheld convergent devices.

- Guenter Weinberger

President and CEO

Sandbridge Technologies Inc.

Article Comments - Architecture options for convergent ...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top