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Bluespec synthesizes SystemVerilog verification assertions

Posted: 01 Feb 2005 ?? ?Print Version ?Bookmark and Share

Keywords:systemverilog? verification? assertion? asic? debug?

Claiming a new capability for chip designers, startup Bluespec Inc. recently announced its ability to synthesize SystemVerilog verification assertions into Verilog 1995 RTL code. That code can be read into verification tools or used to create debugging hardware inside an ASIC.

The Bluespec Compiler, introduced early last year, synthesizes SystemVerilog design assertions into Verilog 1995 RTL. Now it is adding verification assertions as well, and the company claims it is the first behavioral synthesis tool that actually synthesizes verification assertions, as opposed to just passing them through untouched.

Since verification assertions aren't part of a design, it may not be immediately clear why designers would want to synthesize them. But there are several potential reasons, said Shiv Tasker, president and CEO of Bluespec. One is that the resulting Verilog 1995 code can be read by simulators that don't yet support SystemVerilog assertions, as well as by emulators, accelerators and other verification tools.

But another is that synthesized assertions are easier to debug, Tasker said. "We can take that assertion and have it talk directly to configuration status registers, so you can store values and read them out later," he said. Thus, an assertion could serve as a monitor that stores values in a status register and reads them out.

In some cases, said George Harper, Bluespec's VP of marketing, a verification assertion could end up in the ASIC as silicon. For example, he said, someone who designs a bus interface might write assertions describing how other system components would talk to that bus interface. "Because you synthesize to RTL, you can leave that assertion in the ASIC. The chip itself can flag whether it's been properly interfaced to," he said.

Hardware generated from verification assertions might take the form of combinatorial logic, or flip-flops in the case of temporal assertions that occur over multiple clock cycles, Harper said. This hardware is then tied to configuration status registers so that results can be read.

The new verification assertion synthesis capability is available now. The Bluespec Compiler claims 50 to 60 users. The company does not reveal pricing.

- Richard Goering

EE Times





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