Crolles2 alliance pools CMOS process efforts

The Crolles2 alliance partners Freescale Semiconductor, Philips and STMicroelectronics have extended the scope of their joint semiconductor activities to include R&D related to wafer testing and packaging, in addition to the original development of sub 100nm CMOS process technologies.

The agreement reflects the special needs of wafer testing and packaging for devices produced on 300mm wafers in 90nm, 65nm CMOS and beyond. It will look at all aspects of post-fabrication wafer processing including probing, grinding, sawing, die attach, wire-bonding, flip chip and package molding techniques as well as optimization of bond-pad stack design.

The partners will establish a new research laboratory in Grenoble (France) staffed by about 20 scientists and technicians drawn from the three companies. The partners now have more than 1,000 employees working on front-end process development in Crolles, near Grenoble.

The lab will focus on bond-pad stack design and the assessment of low-stress probing, sawing and assembly processes including laser cutting and low-stress molding materials. It will also investigate requirements specification for the next generation of assembly and test equipment. The new Crolles2 alliance assembly and test R&D team will also work closely with key equipment suppliers.

The expansion of the alliance for extended R&D in assembly and test is expected to help the alliance partners remain in-line with the ITRS roadmap for process introduction of assembly and test technology.