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TSMC libraries support Nexsys 90nm production

Posted: 07 Feb 2005 ?? ?Print Version ?Bookmark and Share

Keywords:nexsys 90nm? communications? eda? ip?

Taiwan Semiconductor Mfg Co. (TSMC) has unveiled a full suite of internally developed libraries that support its Nexsys 90nm technology. The TSMC libraries provide accurate links to TSMC technology, supporting design methodologies represented by major EDA, package and IP vendors.

Developed collaboratively between TSMC library development and process development teams, the libraries support the Nexsys general purpose (G), high performance (GT) and low power (LP) processes. The tight library-technology alignment also reduces design time and shortens time-to-market. The libraries cover the full applications spectrum from low-power wireless devices to high-performance communications and computing products.

TSMC's 90nm libraries feature gate densities of 420K gates per mm2, about double the density of the 0.13?m generation libraries. The tapless options allow designers to further reduce leakage power with a back-biasing technique, making them suitable for long battery-life applications. The standard cell libraries also come with a set of engineering change order (ECO) cells that allow for metal-only chip design updates.

The Nexsys 90nm process provides a 2-times gate density improvement, 35 percent faster speed, 60 percent improvement in active power savings and a 20 percent interconnect RC improvement compared to the company's 0.13?m process. TSMC's Nexsys 90nm technology is currently running in TSMC Fab 12, and will be in production at Fab 14 later this year.





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