Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Mentor's Rhines sees programmable IC future

Posted: 07 Feb 2005 ?? ?Print Version ?Bookmark and Share

Keywords:programmable IC? asic? libraries? fpga? pcb?

ASIC design completions are declining and the move to lower process nodes is slowing, said Wally Rhines, CEO of Mentor Graphics Corp., at a keynote speech at the DesignCon conference here Wednesday (Feb. 2). But the good news, he said, is that platform-based design and programmable ICs may help usher in a new wave of innovation.

In an entertaining presentation on "Design in the nanometer age," Rhines noted that the move to 90nmis apparently taking longer than previous process shifts. He observed that 80 percent of design starts last year were at 0.18?m or 0.25?m, with a few people even designing at 1?m or above.

Further, he noted, ASIC design completions are decreasing. "This is a somewhat dangerous trend for those of us in the design industry," he said.

"What will happen is what always happens - we'll move to a new level of abstraction," Rhines said. That next step, he said, will involve a shift to design "platforms" comprised of pre-determined processors, peripherals, intellectual property (IP) libraries, and software.

Yes, there are compromises, Rhines said - but he recalled that when ASICs were first introduced, custom IC designers thought no one would use them, because they didn't have the die size savings or performance of full-custom chips. "Designers accepted the compromise on die size and performance to have faster design times, and it's the same thing here," he said.

Rhines said there will be two kinds of designers in the future - a few thousand who create platforms, and potentially hundreds of thousands who use them to create systems designs. He also noted that systems design is becoming a much larger part of the design process, and that electronic system level (ESL) design is one of the few areas of the EDA industry that's actually growing.

Rhines observed that ASICs still hold an advantage in power, but FPGAs are beginning to provide a suitable alternative in terms of performance and cost. But FPGA design complexity will approach that of ASICs, he said, and will include such challenges as IP integration, timing, hardware/software co-design, prototyping, and PCB integration.

Citing new architectures including structured ASICs, platform ASICs, array-based platforms, and reconfigurable ICs, Rhines said there will be a new generation of products "more customizable" than standard FPGAs.

There were roughly 5,000 people designing custom chips in the 1970's and 50,000 people designing ASICs in the 1990's, Rhines said. He predicted there will be 500,000 people designing FPGAs around 2010. Will we someday reach the point where the total is 5 million? Possibly, Rhines said.

"New architectures will empower people and they will innovate," he said. "That will take us away from the trend of design starts going lower every year, and put us on the road to innovation."

- Richard Goering

EE Times

Article Comments - Mentor's Rhines sees programmable IC...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top