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Intel reveals MIMO radio, dual-core Itanium processor

Posted: 10 Feb 2005 ?? ?Print Version ?Bookmark and Share

Keywords:intel? international solid state circuits conference? isscc? itanium processor? processor?

Intel Corp. will use the International Solid State Circuits Conference (ISSCC) to introduce a dual-core Itanium processor along with one of the first CMOS radio chips using multiple-input/multiple output (MIMO) antenna technology.

The company's CMOS radio project aims to reduce power while enhancing performance. While the end game for CMOS radio development might be a reconfigurable device capable of communicating with a variety of WLANs using different frequencies and protocols, a MIMO antenna system may be the first step toward that goal, said Krishnamurthy Soumya, director for communications circuits research.

Intel's 90nm implementation is effectively a phased-array antenna, he said. The chip uses a "space-time decoder" to interpret signals across four separate planes, and to reconstruct a demodulated bit stream from the combined signals.

The radio chip will increase sensitivity and reduce power consumption for WLAN devices operating up to 5GHz.

While it was possible to utilize a microelectromechanical implementation of MIMO, Soumya acknowledged, Intel's implementation was entirely electronic. Intel's research was performed in conjunction with the University of Washington.

Dual-core processor

Because of its parallel processing capability, the 1.72-billion transistor Montecito chip is said to increase Itanium processor throughput 2.9 times over the single-core version, while reducing the overall power consumption from 130W to 100W.

Reducing power consumption has been a key technology thrust at Intel since the 2001 ISSCC. "It was something of a wake-up call," said Shekhar Borkar, an Intel Fellow and co-director of the company's Microprocessor Technology Lab. Overcoming increased current leakages at 90nm fabrication geometries proved so daunting that Intel placed greater emphasis on power consumption over performance, he said.

Improving performance with a given power envelop has offered pointers to multithreading and multiprocessing. The Montecito device described this week is a dual-core Itanium-2 processor. With each core capable of processing two concurrent threads, and 24MB of cache, the 1.6GHz Montecito nearly triples the throughput of the original Itanium-2 processor (the "Madison"), running at the same clock rate and consuming 30W less.

The reduced power envelop is a consequence of a form of voltage and frequency scaling called "Foxton technology," according to Nimish Modi, Intel VP and GM of the enterprise microprocessor division. Voltage and frequency scaling raisesor lowersprocessor operating voltages and clock frequency in response to the kinds of instruction processing tasks it performs.

A computing-intensive task may require a higher voltage and faster clock speed to loop additions. An address generation, in contrast, takes far fewer cycles to complete.

Foxton technology allows the processor's operating voltages to be adjusted up or down in up to 32 increments; its clock frequency can be adjusted over 64 increments. As with the Pentium and other Intel processors, the operating voltage is adjusted by an external voltage regulator in response to a 5bit voltage identifier code generated by the processor. The clock frequency is adjusted by an internal voltage controlled oscillator and divider network from a fixed 1.6GHz clock input.

- Stephan Ohr

EE Times

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