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Toshiba unveils high-density DRAM with floating-body cells

Posted: 11 Feb 2005 ?? ?Print Version ?Bookmark and Share

Keywords:128Mb? silicon-on-insulator? dram? soi wafer?

Toshiba Corp. has developed 128Mb silicon-on-insulator (SOI) DRAM with floating-body cells that the chip maker claims will help usher in embedded DRAM chips on SOI wafers.

Toshiba reported at the International Solid-State Circuits Conference on Wednesday (Feb. 9) that the high-density DRAM achieved an 18.5 nanosecond access time.

"Various results [for floating-body cell technology] have been reported, but no high-density memory has yet been reported," said Takashi Ohsawa of Toshiba's SoC Research & Development Center. "Engineers are questioning whether a practically operating floating-body cell memory with hundreds of megabits density can actually be fabricated. Our work has realized a memory with such high-level density."

Floating-body cell memory is considered nondestructive, but reports surfaced in 2002 that charge pumping caused data deterioration. The memory cell is not as fully destructive as in conventional DRAMs, but is slightly disturbed by charge pumping.

Toshiba engineers dubbed this characteristic "quasi-destructive," and sought to utilize these characteristics to lower the memory's power consumption.

Toshiba's DRAM uses a 6F2 (F=0.165 micron) floating-body cell. At this scale, about 1,000 holes in the cell contribute to the difference in electrical current that determines "data 1" or "data 0." A cell with about 1,000 holes reads out as "1."

An average of up to two holes is eliminated from the cell with every pumping cycle. This occurs because one or two electrons are trapped at the Si-SiO2 interface state during inversion, and many holes recombine with the trapped electrons during accumulation. Thus, data 1 is destroyed by the charge pumping after about 100 word-line cycles.

Since a few holes have to be replenished in the data 1 cell with every word-line pumping, the Toshiba engineers devised a structure in which each bit line used a sense amplifier operating asymmetrically. Conventional DRAMs also use a sense amplifier at every bit line, but they operate symmetrically.

There are three different sense amplifier modes: no operation for data 0 cells; a long, strong drive on cells to be written as "1;" and a short, weak drive on data 1 cells for replenishment.

By limiting full driving to cells to be written as data 1, both write and refresh power were reduced by an average of about 50 percent, Ohsawa said.

To achieve full functionality using high-density floating-body cell memory, Toshiba said it is essential to generate a reference voltage to determine data 0 or 1. A reference voltage is usually generated by a pair of data 1 and 0 dummy cells. To obtain a peaked, accurate reference voltage, Toshiba implemented 256 dummy, 128 data 1 and 128 data 0 cells. This "multiaveraging dummy cell system" revealed that a 2-Mbit memory had a cell with 40 mV signal with a random access time of 18.5 nanoseconds.

Toshiba said cell size was 0.17?m2 (0.33?m-by-0.515?m) with six-metal wiring based on 90nm technology. The chip size is 7.6mm-by- 8.5mm.

Based on the successful simulations, Toshiba engineers said they are fabricating a prototype of a 128Mb DRAM and expect to report their results later this year.

- Yoshiko Hara

EE Times

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