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SRAMs readied for 45nm node

Posted: 14 Feb 2005 ?? ?Print Version ?Bookmark and Share

Keywords:sram? 90nm? virage logic? 45nm? soc?

Issues like soft errors and gate current leakage are emerging as design challenges as SRAM technology moves below 90nm, according to memory experts at this week's International Solid-State Circuits Conference here.

Designers from IBM, Samsung, Texas Instruments and Virage Logic laid out design, test and process issues affecting SRAMs in sub-90nm devices during a panel session. The next threshold is the 65nm process node, and challenges increase substantially at the 45nm process node.

As transistor geometries shrink, soft errors have become a much bigger issue in SRAM design. Soft errors are caused when neutrons, alpha particles or other ionizing particles strikes a solid-state memory. Each can degrade stored data in the memory cell. Below 90nm, that phenomenon becomes a critical concern. With ever-increasing wafer costs, companies can no longer afford to spin multiple silicon shuttles.

Gate current leakage has also become a critical concern for power-aware systems. IBM's Harold Pilo addressed the Vt variations and how to counter them. Emerging trends such as random Vt variations, decreased Ion/Ioff and increased gate leakage are driving changes in design style and architecture.

Yervant Zorian of Virage Logic offered test solutions to improve SRAM yield. He said 90nm semiconductor fabrication processes allow for the creation of complex SoCs, including embedded SRAM cores with very large aggregate bit counts. "Unfortunately, this results in defect susceptibility levels that increase test escapes and reduce process yield," said Zorian.

TI's Robert Baumann warned that reductions in circuit operating voltages, aggressive substrate/junction engineering and reductions in node capacitance mean radiation-induced single event effects have become a serious threat. "Unchecked, errors from single event effects have the potential for inducing the highest failure rate of all other reliability mechanisms combined," Baumann said.

Samsung's Soon Moon Jung said growing chip density has caused rapid reductions in gate lengths and gate oxides dimensions in CMOS transistors, which has been accompanied by leakage current increases. "The suppression of the leakage current in a MOS transistor is a most difficult challenge when the gate length and threshold voltage are reduced to satisfy the low-operation voltage and the high performance needed," said Jung.

Meanwhile, NEC has developed an SRAM with characteristics that promises to keep pace with the scaling of CMOS logic at the 45nm process node. The dynamic voltage-scaling technique decribed by NEC researchers here ensures that SRAMs exhibit the same delay dependence on Vdd as do CMOS logic circuits.

Minimum supply voltages for SoCs are limited by onboard SRAMs. This is because with decreasing supply voltage, SRAM delay increases at a higher rate than CMOS logic circuit delays. Also, read operations at low-Vdd levels result in stored-data destruction in SRAM cells. Data destruction may occur even at normal-Vdd levels due to increased transistor mismatch that accompanies geometry scaling. Techniques for boosting Vdd in SRAMs have been proposed as a way to achieve both higher-speed data access and more stable data retention during read operations.

These boost techniques result in a deterioration of transistor reliability. NEC avoided boosting techniques and instead included one additional transistor than the usual six to optimize delay dependence. This increases a typical cell block area by only 11 percent over conventional SRAM blocks of the same configuration.

- Nicolas Mokhoff

EE Times

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