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Users laud C design in DAC 'trip report'

Posted: 15 Feb 2005 ?? ?Print Version ?Bookmark and Share

Keywords:design automation conference? synopsys? ic layout? cynthesizer?

Engineers are warming to C language design tools, according to reviews in the Design Automation Conference (DAC) &quote;trip report&quote; released Friday (Feb. 11) by industry gadfly John Cooley. In the report, 368 engineers provided detailed reviews of chip design tools from dozens of vendors.

As in previous years, the DAC 2004 "trip report" consisted of hands-on reviews from engineers, some of whom attended last year's Design Automation Conference. The report is available on Cooley's Deepchip web site.

In previous trip reports, and in the E-mail Synopsys Users Group (ESNUG) mailings compiled by Cooley, most of the comments about C language design have been strongly negative. Not so in the new report, where several engineers expressed interest and provided positive reviews of Forte Design Automation's Cynthesizer product.

One Japanese engineer commented that Cynthesizer met all four of his criteria - support for pipelined design, ease in defining interfaces, tool processing speed and throughput, and quality of design. Another said it does an excellent job on complex data transformations, while a third said "they still need to work a little bit to have some stable results on large blocks."

Mentor Graphic's Catapult C product attracted commentary from several users and some interested evaluators. "It does exactly what it says it does; translate C to RTL," said one. But this user also said the tool is "more buggy than most EDA tools I've used." Celoxica's DK Handel-C synthesis, however, received some skepticism.

This DAC trip report was the first in which Cooley asked questions about Matlab and Simulink from The Mathworks, and he got a number of responses. "Matlab and Simulink are everywhere, and hardly anyone talked about SPW [CoWare Signal Processing Worksystem]," Cooley wrote.

Other highlights from the DAC trip report:

  • Engineers liked Synplicity Synplify Pro and ASIC tools, were impressed with Synplicity's Identify debugging tool, and offered pro-and-con reviews of Mentor Graphics' Leonardo and Precision FPGA design tools.
  • There's interest in structured ASICs, even though Cooley described them as little more than gate arrays.
  • Magma Design Automation's Blast Create synthesis tool is attracting some interest.
  • A lengthy review pitted ReShape's pdOptimizer IC layout automation tool against Cadence Design Systems' First Encounter. ReShape competitor Manhattan Routing received several reviews.
  • Users like Apache's RedHawk IR drop tool and seem to prefer Cadence Design Systems' CeltIC over Synopsys' PrimeTime-SI.
  • Fishtail's Focus, a tool that generates false and multicycle paths, won strong support.
  • Silicon Canvas Laker is emerging as a strong competitor to Cadence's Virtuoso custom layout system.
  • Engineers appear to prefer Nassda's HSIM circuit simulator over other alternatives.
  • Sandwork's Spice Explorer, a Spice "lint" tool, received strong recommendations.
  • Little was said about design for manufacturability (DFM) other than a few comments about ChipMD.
  • Newcomers Orora and CiraNova received attention in reviews of analog synthesis tools.
  • Finally, unannounced startup Accelicon was lauded for having "the most impressive new tool for analog layout transistor level floorplaning presented at DAC 2004."

    - Richard Goering

    EE Times





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