ST SoC reduces overall cost/channel

STMicroelectronics' (ST) new SoC device combines two quad-MAC ST140 dsp cores, a standard ARM926-EJS risc processor core providing a total of 29,000Mops, 7,500Mips, 4800MMacs/s, 16Mb of embedded SRAM memory, dedicated Turbo Decoding Engine (TDE) for Data error correction, and Convolutional Decoding Engine (CDE) for Voice error correction for 2.5G and 3G standards, with a complete set of high-performance peripherals.

Engineered for use in wireless infrastructure equipment, the new chip (called GreenSIDE) offers an opportunity to reduce the overall cost/channel and cost/MIPS. According To ST, this device was defined in cooperation with leading wireless-infrastructure manufacturers to outperform the existing 2.5G and 3G baseband modem solutions.

Fabricated using ST's 130nm high-performance CMOS technology, the GreenSIDE architecture, being fully modular, can be easily and quickly customized with the addition or removal of peripherals or logic blocks to increase its efficiency in certain specific customer applications.

The included TDE and CDE are fully-compliant hardware accelerators of the required channel-decoding algorithms specified in the 3GPP and 3GPP2 specifications. Capable of decoding voice and data channels for the W-CDMA, cdma2000 and EDGE standards, both coprocessors are tightly coupled to the on chip direct memory access (DMA) to accelerate the data transfer. The CDE can decode up to 256 AMR (Adaptive Multi-Rate) voice channels, while the TDE can decode up to eight 384Kbps data channels.

ST offers a complete set of development tools around the GreenSIDE product to evaluate the performance, and to develop, debug and integrate Application Code on the chip via an ARM/DSP environment, providing multi-Core Development/Debug capabilities.

Sample devices and evaluation boards are already available. Volume production will start mid-2005, with pricing expected to be in the $1 per channel range.