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Timing analysis needs overhaul, speaker says

Posted: 03 Mar 2005 ?? ?Print Version ?Bookmark and Share

Keywords:ic device? eda? analysis tools?

New IC devices, circuits, and physical effects will drive a new generation of timing analysis tools, said David Hathaway, senior technical staff member for EDA at IBM Microelectronics, at a keynote speech at the Tau timing workshop here Monday (Feb. 28). Hathaway said that timing analysis needs to become more pro-active, incremental, and statistical.

Tau is a small but influential ACM/IEEE workshop on timing issues in digital systems. Hathaway's talk, entitled "A brief history of timing," first reviewed many years of delay modeling and timing analysis, and then discussed current and future challenges.

24 years ago, Hathaway recalled, "timing analysis was really easy." It was good enough to assume a 20ns constant delay per gate. That didn't last long. Over time, designers were forced to consider load-dependent delays, slew dependence, resistance-capacitance (RC) delays, coupled delay models, and delay variability.

Static timing analysis was "one of the major triumphs of EDA," Hathaway said, "because we were lucky." He noted that it separates topology from function, thus providing an efficient analysis, and it avoids an exponential blow-up due to sensitivity dependencies.

But now, he noted, "our luck is running out." Block-oriented techniques are primarily used today, Hathaway noted, because path-oriented analysis can lead to exponential path tracing. But a purely topological approach can be too pessimistic, requiring some selective path tracing.

Meanwhile, variable parameters such as oxide thickness are driving the need for statistical timing analysis, Hathaway said. But he identified several challenges facing statistical analysis. One is that block-based methods can have accuracy problems, because statistical variations depend on paths.

Power supply noise, simultaneous switching, and wire coupling are all becoming important factors in statistical timing analysis, Hathaway noted. "Delays depend on things that might not occur on the path," he said. "The safe approach is to assume that all bad things happen together, but you can't close timing that way. So you assume a limit on the number of bad things that can happen."

Hathaway made a strong pitch for incremental timing analysis, which makes it possible to handle small changes efficiently. One way to implement that, he said, is through "lazy evaluation" methods that only re-run the analysis in critical areas, and only when changes are really needed.

In a provocative statement, Hathaway said that we don't really have timing-driven design today. "We have timing-influenced design," he said. "For true timing-driven design, we would need to have the timer take control and identify problems. Don't make the optimizer initiate the query."

One future challenge, Hathaway said, is developing "relative" statistical timing analysis. He noted that timing tools today compare expected values on a path, rather than looking at what happens if a reference structure changes. For example, he noted, a timing analyzer should be able to answer such questions as: if I run this ring oscillator this fast, how fast can I run the rest of the chip?

Conference chair Dennis Sylvester asked how statistical timing users can get models if they don't happen to be IDMs. "The modeling and data that goes into a statistical timing engine is at least as difficult as the timing engine," Hathaway said. "No one will give you the statistical data until you can do something with it."

"But I really believe that if we're going to push smaller geometries, we don't have a choice," Hathaway said. "We'll have designs so pessimistic that if we don't do this, we'll hit a brick wall."

- Richard Goering

EE Times

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