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ST flash memory chip tailored for 3G mobile phones

Posted: 04 Mar 2005 ?? ?Print Version ?Bookmark and Share

Keywords:stmicroelectronics? st? nor flash memory chip? memory chip? m30l0r8000x0?

STMicroelectronics (ST) rolled out a 256Mb NOR flash memory chip that uses a 2bit/cell architecture to provide increased memory density in a small-sized die. The new M30L0R8000x0 is the first of a series of 2-bit/cell devices that also includes a 128Mb IC, with a 512Mb chip currently in development.

Designed for high-performance code execution and data storage, the 256Mb device is specifically targeted at the third-generation (3G) mobile phone market, where increasingly sophisticated applications and multi-function capability are demanding large amounts of memory in a small physical footprint, said ST.

The M30L0R8000x0 is produced using the company's 0.13?m process technology, and uses a compact chip-scale 8-by-10mm TFBGA (Thin, Fine-Pitch Ball Grid Array) package. It is intended for operation on a 1.8V power supply (and also available with 3V I/O) for low power consumption and compatibility with the latest mobile-phone designs.

In addition, the new memory chip maintains software compatibility with earlier 1-bit/cell products, and all additional processing required by the multi-level cell technology is handled on-chip. It is configured in an asymmetrical block architecture, divided into 16Mb banks, with a flexible block-locking scheme; fifteen of the memory banks each contain 16 main blocks of 64K words, while a parameter bank contains 15 main blocks plus 4 parameter blocks. The Parameter Blocks are located either at the top of the memory address space (M30L0R8000T0) or at the bottom (M30L0R8000B0).

The Asynchronous Page Read Mode allows a consecutive-word read access time of 20ns, while in Synchronous Burst Read Mode, data is output on each clock cycle at a frequency of up to 66MHz. Burst Reads can cross bank boundaries and can be suspended and resumed. According to the press release, the multiple bank architecture of the M30L0R8000x0 allows Dual Operations, with Read operations possible in one bank while another is Erased or Programmed, and no delay between read and write.

Each block can be erased separately. Erase can be suspended to allow a Program or Read operation in another block and then resumed. And Program can be suspended to allow data to be read from any memory location except for the one being programmed. Additionally, each block can be programmed and erased through more than 100,000 cycles.

The memory's command set is consistent with the JEDEC Common Flash Interface (CFI), the industry-wide protocol that ensures compatibility between Flash memories. Security features include a 64-bit unique device number programmed during manufacture and a 2112-bit user programmable OTP (One-Time-Programmable) cell. To conserve power in mobile applications, this new product features an Automatic Standby mode, switching to Standby when the bus is inactive during Asynchronous Read operations.

The M30L0R8000T0/B0 is available in the TFBGA88 8-by-10mm, 0.8mm-pitch package in volume production, with a selling price of $10.

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