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Fraunhofer IIS selects Mentor Graphics Catapult C Synthesis tool

Posted: 10 Mar 2005 ?? ?Print Version ?Bookmark and Share

Keywords:fraunhofer institute for integrated circuits iis? catapult c synthesis? digital broadcast?

Mentor Graphics Corp. announced that the Fraunhofer Institute for Integrated Circuits IIS has selected the Mentor Graphics Catapult C Synthesis tool for use in next-generation digital broadcast applications. Fraunhofer IIS chose the Catapult C Synthesis tool based on quality of results, time savings, ease of use, and the tool's compatibility with the company's C/C++ design flow.

"During our evaluation, we found Catapult C's quality of results and ease of use to be very convincing. Using the tool, we expect a 5 to 10 times improvement in productivity for algorithmic blocks, compared to HDL synthesis," said Frank Mayer, design manager, Fraunhofer IIS. "The Catapult C tool's ability to use pure C code as input fits very well in our design flow, allowing us to automatically generate hardware directly from our untimed C/C++ system models regardless of the target technology. Based on the success of our evaluation, we deployed Catapult C in production design projects."

Fraunhofer IIS develops digital broadcast applications that depend on complex digital DSP algorithms. The organization typically implements the full system in FPGA as a prototype for real-time performance validation before retargeting the design to an ASIC for production. Manual register-transfer level (RTL) creation for FPGA prototypes and ASICs were found to be too inefficient and error prone, and left no time for design space exploration. This triggered the decision to explore high-level synthesis to reduce manual development time and validation effort.

The Catapult C Synthesis creates RTL that can be synthesized into gates using standard RTL synthesis products, enabling it to fit within a wide variety of tool flows.

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