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Panelists peer into future of FPGAs

Posted: 10 Mar 2005 ?? ?Print Version ?Bookmark and Share

Keywords:fpga? processor? microprocessor? vhdl? sram?

Where will FPGA design be in 2010? Panelists from leading FPGA vendors offered differing conclusions at the Easy Paths to Silicon seminar at the Embedded Systems Conference in San Francisco Monday (March 7).

Panelists generally agreed that low-cost FPGAs will be a strong market driver, but sparred over SRAM versus flash-based devices. They discussed such problems as leakage power and soft errors, and concluded that soft processors and reconfigurability will grow in importance.

Moderator Bryan Lewis, research vice president and chief analyst at Gartner Dataquest, started the discussion with some market figures. He said the PLD/FPGA market is around $3 billion now and is expected to double by 2010. Lewis said design starts peaked at over 100,000 in 2000, are now around 80,000, and will be over 100,000 once again by 2010.

But it won't be deju vu all over again. By 2010, over one-third of all PLD/FPGA devices are expected to have microprocessor cores, up from about 15 percent today, Lewis said.

Consumer and automotive applications will be the strongest drivers for the FPGA market, said Yankin Tanurhan, senior director of applications at Actel Corp. "Low-end markets will be the driving forces for FPGAs over the next 10 years, and that's where we're investing heavily," he said.

Gordon Hands, strategic marketing manager at Lattice Semiconductor Corp., said there's been a recent switch in which customers seem most concerned about reducing costs. Robert Blake, vice president of product planning at Altera Corp., said his company sees both low-end and high-density markets as very important.

Blake observed that leakage current is a significant problem for devices at 90nm and below, and he said there will be tools that can help users trade off performance and power. Tanurhan then jumped in to say that the power picture for SRAM-based devices "doesn't look that good" due to high currents. He said that flash-based FPGAs will offer a considerable power advantage.

These statements brought about immediate retorts from both Hands and Blake. SRAM does cause a small increase in current, but it's insignificant, Blake said. He noted that Altera's 0.18 micron Max II devices use both SRAM and flash techniques, but he said that flash doesn't work with leading-edge technologies.

"Flash is one to two generations behind in technology. You can afford it if chips are small and dominated by I/O," he said.

The real solution to power problems, said Lawrence Getman, director of embedded marketing at Xilinx Inc., is partitioning and selective hardening of functions on the chip. "If you want to get to the logic density you need, you need to go to SRAM technologies," he said.

Another problem that's emerging in FPGA design is soft error rates. Blake said that new design techniques will make cells more robust, and that some customers are moving to structured asic solutions to avoid such problems. But for Tanurhan, it was one more argument for flash-based FPGAs. "We're the only company that really has solutions in this area," he said.

One area where the panelists generally agreed was the growing importance of soft processor cores. Getman noted that they're "gaining a lot of acceptance" among Xilinx users. Blake said the use of soft processors has reached "critical mass" at Altera. But he said the tool flow must expand to become more comfortable for software developers.

"Today you have to write VHDL or Verilog to get performance and capability," he said. "I think we'll start to see that change."

Panelists also generally agreed on the growing importance of in-system reconfigurability. "It's not a question of whether devices will have reconfigurable fabric on them, it's a question of how much," said Getman.

- Richard Goering

EE Times





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