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Net processor seeks to run triple play

Posted: 16 Mar 2005 ?? ?Print Version ?Bookmark and Share

Keywords:sinett? wlan? wireless lan? oneedge? processor?

The triple intersection of network security, packet processing and wireless-LAN (WLAN) integration with wired infrastructure has been probed by numerous semiconductor designers. This week, a network processor startup takes its turn at combining features from the three worlds.

SiNett Corp., a newcomer with headquarters in Sunnyvale, Calif., and a significant base in Bangalore, India, is introducing separate families of its OneEdge processor for WLAN switch markets and for access aggregation systems. OneEdge uses a licensed MIPS core not as a control plane processor, as is common in NPU designs, but as an assistant to the chip's hardwired data path elements. Four MIPS cores are implemented in a multicore Embedded Processing Engine Cluster, while data path functions are designed in a full-custom block that SiNett calls the Hardware Pipe.

The concept can be used more in solving the merger of WLAN and enterprise wired LANs than in handling general network-processing tasks. Joseph Byrne, principal semiconductor analyst at Gartner Research, said that SiNett is the first company with a packet-processing perspective to address security and WLAN integration. However, he said, "competitively, they will find it a tough market as larger switch players like Broadcom and Marvell offer integrated devices."

Shrikant Sathe, VP of marketing and operations at SiNett, said that the founders' experience at previous networking companies such as Maverick Networks Inc. convinced SiNett's design team that first-generation architectures in both WLAN switching and security processing had to be reconsidered.

When OEMs offered WLAN switches and single-box appliances, Sathe said, an FPGA acted as the control glue between a Layer 2/3 Ethernet switch, a network processor and a security processoran architecture SiNett calls "ping-pong," because of the way packets are bounced around for header processing. The new role of the wireless-LAN mesh is not as an overlay, but as a LAN subnet directly integrated into the enterprise LAN and WAN access systems. This means that core architectures can't be unwieldy multichip lookaside engines, but must be integrated switch processors dedicated to multiple functions using multiprocessors.

SiNett's designers took a tabula rasa approach to the problem. In the mobility category, SiNett created a concept called "queue attachment," in which a central pool of packet queues could be assigned dynamically to any port for any traffic flow requiring faster buffering. This implied having a large number of configurable queues and using a fine granularity of bandwidth provisioning.

In December, SiNett chose the MIPS architecture as its key for Embedded Processing Engine Clusters which were tied to SiNett's own crypto engines for encryption and secure tunneling support. Four MIPS processors are used in each cluster, though they are dedicated to a single-threaded data path task, not to multithreaded operations.

The on-chip Hardware Pipe integrates such functions as Layer 2 and 3 switching, 802.11 and 802.11e packet processing, virtual private network termination at both IPSec and SSL levels, mobility management, traffic shaping and access control list management.

Two families of processors have been defined, the SN5xxx for WLAN switches and Layer 2 switches, and the SN6xxx for WLAN appliances and service cards requiring larger-bandwidth aggregator channels. The first two chips will be the SN5024, with 24 ports of standard Ethernet and four uplinks; and the SN6004, with four Gigabit Ethernet ports for higher throughput. The chip handles all major WLAN protocols, including WEP, WPA and WPA2.

- Loring Wirbel

EE Times




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