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Formal tool able to verify false paths

Posted: 21 Mar 2005 ?? ?Print Version ?Bookmark and Share

Keywords:real intent? prover? design automation and test in europe? date? puretime?

Promising to save designers from a lengthy manual review cycle, Real Intent Inc. rolled out a software timing-exception prover at the Design Automation and Test in Europe conference in Munich, Germany. Real Intent's PureTime verifies false and multicycle paths.

To reach timing closure, designers identify false and multicycle paths using synopsys design constraint (sdc) files. These timing exceptions guide timing and synthesis tools that would otherwise waste time trying to optimize those paths.

There have been some recent moves to automate the generation and verification of timing exceptions. Startup Fishtail Design Automation Inc. offers Focus, a tool that generates timing exceptions, and formal-verification provider Averant Inc. announced SolidTC, a tool that verifies timing exceptions, in January.

Prakash Narain, Real Intent's founder and CEO, noted that designers usually have to go through a manual review process to verify that the exceptions are correct. "It's a hazardous methodology," he said, "because the timing exceptions don't necessarily relate to the logical behavior of the design. The related dynamic behavior is very difficult to grasp."

Like SolidTC, PureTime takes in register-transfer-level (RTL) code and SDC files, and promises an exhaustive proof of the timing exceptions. PureTime is based on Real Intent's Verix formal analysis engine, but is a standalone offering that doesn't require Verix.

Narain said he was unaware of any competing offerings, but he said that PureTime has several distinctive features. First, he said, it provides a "unique hierarchical methodology" that has successfully analyzed designs with up to 10 million gates. Narain also said it can verify exceptions at both the RTL and netlist levels.

If PureTime determines that an exception is correct, Narain said, it reports a counterexample to help guide the designer to the exact location and time where the problem occurred in the design. It also produces a VCD format trace for debugging tools, he said.

PureTime supports both VHDL and Verilog. It is due to ship in the third quarter, priced starting at $100,000 for a one-year term license.

- Richard Goering

EE Times




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