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Four industry players team up to address power issue

Posted: 24 Mar 2005 ?? ?Print Version ?Bookmark and Share

Keywords:silicon design chain initiative? power management IC? Design Silicon Chain Initiative? arm cadence tsmc?

One resounding plea can be heard from various IC design labs all over the world and that is for chip designers to address power management issues. Unless this nanometer-scale design kink is resolved, huge market opportunities can and will be lost. "In 2005 and beyond, power management will no longer be just a niche issue as it will be a mainstream issue that we need to address," said Mike McAweeney, Group Director of Strategic Third Party Programs for Cadence US.

In response, members of the Silicon Design Chain Initiative (SDCI) announced silicon-validated, low-power design techniques that promise to achieve power savings of over 40 percent on a 90nm test design. Members of the SDCIApplied Materials Inc., ARM, Cadence Design Systems and Taiwan Semiconductor Mfg Corp. (TSMC)developed an integrated power management methodology that optimizes SoC power and performance, with minimal disruption to existing RTL flows, said the press release. The low-power design employed an ARM1136JF-S test chip, ARM Artisan standard cell libraries and memories, Cadence Encounter design platform, and TSMC's Reference Flow 5.0.

During a pre-briefing with representatives from ARM and Cadence, McAweeney shared that the focus of this collaboration was "to first yield a low power design flow infrastructure that can easily be adopted by the mainstream; second, to prove that low power design flow by comparing it against a nominal flow; and third, to manufacture it."

Dynamic, leakage power
To reduce power consumption on the ARM1136 design, both leakage and dynamic power needed to be addressed. The team first decided to tackle dynamic power consumption. They determined which parts of the design could have their voltage reduced (voltage scaling), and then partitioned the design into voltage domains or voltage islands.

In this type of multi-supply voltage (MSV) design, each domain operates at a different supply voltage depending on the timing characteristics, explained the companies. The design team chose to keep the blocks that are timing critical in one domain operating at 1V, and the less timing critical blocks were grouped into a second domain, with the voltage scaled down to 0.8V.

However, when using voltage scaling, there is a need to translate the voltages for the signals that interface between voltage domains. This is done by inserting level shifters. "Previously, customers have been reluctant to take advantage of this technique because inserting level shifters was a manual and error-prone effort," said McAweeney.

Cadence and Artisan worked together to create level shifters optimized for use with the Cadence Encounter NanoRoute routing engine.

Additional dynamic power reduction was achieved through clock gating. Clock gating is the turning off portions of the design that are not in use. For the ARM1136 design, 85 percent of registers were gated.

The next problem addressed was leakage power. As transistor lengths have gotten smaller, leakage currents have become a significant source of power consumption, said the four companies. The team used libraries from Artisan that contained a matched set of logic cells, each having different threshold voltages (Vt) and the same physical footprint. Cells with higher threshold voltage leak less than their counterpart cells with lower Vt.

However, High-Vt cells run slower than low Vt cells. To meet the 350MHz performance goal while minimizing leakage current, the team first optimized the design during synthesis using Cadence's Encounter RTL Compiler, which can take advantage of the two different sets of threshold voltages in the library. "That is the unique feature of our Encounter RTL Compiler," said McAweeney. "Other system tools in the market will optimize power, performance and area separately, while we do it simultaneously, which gives us the best results."

Analysis and verification
Once power was optimized, the team needed to perform analysis and verification of its design. They used the Effective Current Source Model (ECSM) that, unlike traditional modeling which models voltage, models the current drawn by the transistors. The ECS-based standard cell models used in the test chip achieved delay prediction that correlated on average to within 0.5 percent of SPICE. "Apparently," McAweeney said, "traditional non-linear delay models provided a lot of inaccuracies."

40.3 percent power savings
The new low-power design from the SDCI reportedly achieved a 37.9 percent improvement in dynamic power and a 46.7 percent improvement in leakage power for a total savings of 40.3 percent. However, George Kuo, Technical Director of Design Chain Initiatives for Cadence US, stressed that this figure is not the only value savings that they have achieved with this project. "The other half of value savings is through all those automation that we have used," Kuo said.

Susan Runowicz-Smith, Director of Business Development of Design Chain Initiatives for Cadence US, added, "Through this collaboration, we are helping the industry ramp to volume the advance processes faster, which will consequently translate into cheaper parts faster."

So after the power management issue, what's next for the SDCI? "Design for test and design for manufacturability or yield optimization is another big issue for our customers," answered McAweeney. This we will look forward to.

- Margarette Teodosio
Electronic Engineering Times-Asia




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