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Altera faces challenges with well-developed products

Posted: 28 Mar 2005 ?? ?Print Version ?Bookmark and Share

Keywords:programmable logic devices? iic-china?

Altera's Asia-Pacific Marketing Director Louie Leung

With electronics in Asia moving up the value chain, programmable logic devices provider Altera is positioning itself by refining its product portfolio. The company will take part in the coming International IC-China Conference & Exhibition (IIC-China) in Shenzhen, Beijing and Shanghai beginning April 4 to meet the increasingly demanding needs of Asian EEs.

Asia-Pacific Marketing Director Louie Leung, said, "One of our challenges is to increase our awareness in our applications particularly in the digital consumer market. We need to increase our awareness through all sorts of channels including prominent trade shows like IIC-China."

Altera sees its opportunities in consumer market technologies, which have been overwhelmed with innovative ideas, increased feature sets and short product life cycles. Programmable logicspecifically low-cost FPGAis playing a strategic role where it enables technology advances and flexibility in digital consumer products to move at a faster pace than traditional ASIC and application-specific standard product (ASSP).

Development platform
Programmability and reprogrammability are by definition delivering short design cycles and therefore lower development costs. Traditional ways of using ASSP or ASIC are being squeezed but using ASSP does not create differentiation.

"Because of the rapidly rising cost of IC development, chances are high that features offered by ASSP overshoot or undershoot for a particular end product. The same rising cost for IC design is applicable to ASIC. Days are limited that any major ASIC supplier can offer low or no NRE (amortized over quantity) because a 0.13?m (or below) program can easily cost $500k and above. This type of investment requires the ASIC to create revenue of $10M and above for any reasonable internal return. The digital convergence is fragmenting the end market and a product with a super high run rate is hard to come by these days," explained Leung.

Altera's PLD (MAX II and Cyclone/II families) and structured ASIC with FPGA front-end (Hardcopy/II) help design engineers to accelerate project development time. With the shortened development time, engineers actually have more time to improve the quality through system engineering, or can even introduce new incremental features in a short time."

Design activities in China
There is a need in China's semiconductor industry for the creation of the design and manufacturing in the country. Through participation in IIC China, Altera would like to spread the message to design engineers that programmable logic devices are the most suitable platform for them to take a design concept and implement it for proof of concept in the shortest possible time.

"In the past, China did not have a big pool of logic design engineers and it is the mission of Altera to build this talent up. The knowledge and usage of PLD will help the proliferation of the logic design capability in China. PLD is also an express ticket to full blown IC design. PLD can jump start the logic design capability in China and therefore pave the way for a bright future in PLD demand. More importantly, Altera extends the capability of PLD into Structured ASIC, especially in the ultra deep submicron area."

As the industry heads to an era where system-on-a-programmable-chip defines customers' designs, and that complex technology requirement, mounting time-to-market pressures and higher development cost, system manufacturers continue to look for alternatives.

"At IIC, Altera believes there is a need to equip engineers to address the challenges in 90nm technology, devices, tools and IP. Through the forums and seminars, Altera will impart in the integration of programmable logic, memory, high speed I/O and mixed signal circuitry in a system specifically leveraging their solutions in designs, which will significantly lower overall system cost and ultimate time-to-market," said Leung.

Kathryn S. Gerardino
Electronics Engineering Times- Asia




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