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'Concurrent' IC design suite rolls

Posted: 30 Mar 2005 ?? ?Print Version ?Bookmark and Share

Keywords:ic physical design? synopsys? ic compiler? physical compiler synthesis? astro placement?

Proclaiming the "next generation" in IC physical design, Synopsys Inc. rolled out IC Compiler, which concurrently runs physical synthesis, clock tree synthesis, placement, routing, yield optimization and signoff correlation.

IC Compiler incorporates the functionality in Synopsys' Physical Compiler synthesis and Astro placement and routing products. It does not include the Design Compiler synthesis tool, and is thus not an RTL-to-GDSII solution. It is, however, clearly aimed at competing with magma design automation's blast fusion, which also rolls physical synthesis, placement and routing into a single tool, as well as Cadence Design Systems' SoC Encounter platform, which combines synthesis with IC physical design.

In his keynote at the Synopsys User's Group (SNUG) meeting last week, Synopsys CEO Aart de Geus said the company has already done a great deal of work in "correlating" internally developed products such as Physical Compiler and the Primetime timing analyzer with those acquired from Avanti, including Astro and the Jupiter floor planner. That work, he said, was largely completed by 2004.

Parallel effort

"There was a parallel effort to work on the next generation, which is not only correlation but being able to concurrently deal with many issues that need to be handled in design," De Geus said. That's crucial at 90nm and below, he said, because timing, power, area, signal integrity and yield all need to be optimized together.

"Current solutions have a limited horizon because they treat problems sequentially," said Antun Domic, SVP of Synopsys' implementation group. "They do placement, then clock tree, then routing, and then they make corrections." That does not work, he said, given the design sizes, routing layers, resistance variation, clock tree resource consumption and via resistance in leading-edge chip designs.

Domic called IC Compiler the "centerpiece" of Synopsys' Galaxy IC design platform, which includes Design Compiler. There are three new technologies in IC Compiler, he said: "extended" physical synthesis, signoff-driven closure and yield optimization. Whereas physical synthesis in the past has included placement, extended physical synthesis claims to extend synthesis to routing. "We can do corrections with the full postroute data available," Domic said. That improves the quality of results and reduces the number of design iterations, he said.

Signoff-driven closure means that IC Compiler shares common libraries, constraints, delay calculation, extraction and regression tests with two widely used signoff tools, PrimeTime and Star-RCXT. Beyond that, IC Compiler links directly to those products and provides signoff data to drive incremental optimizations in final stages.

The result, said Domic, is "signoff-driven optimization for all design objectives, across multiple modes and corners."

Yield enhancement technologies in IC Compiler include yield-driven physical synthesis, multicorner optimization, power-aware placement, preferred routing rules, via minimization and redundancy, timing-driven wire spreading, timing-driven metal fill, critical-area-driven routing and lithography-aware routing. Synopsys also claims to forward "design intent" data to resolution-enhancement technology tools.

Other IC Compiler capabilities include physical test, low-power support, hierarchical and flat floor planning, chip finishing, automatic macro placement and power network design. The tool offers a new "photorealistic visualization" utility called TrueVue and supports the TCL scripting language.

Major re-architecting

Domic said that IC Compiler is a "major re-architecting" of Physical Compiler and Astro, built on an "extended" version of Synopsys' Milkyway database. Third-party tool integration is provided through standard data formats.

Stephen Meier, VP of Synopsys' R&D implementation group, said that perhaps 30 to 40 percent of the code in IC Compiler is new. It's a "unified system" that leverages a single data model, Meier said. The Milkyway database was enhanced, he said, to handle synthesis attributes and constraints.

Meier said that IC Compiler has some capabilities for design rule checking but is not meant to be a replacement for a full-chip DRC product, such as Mentor Graphics Corp.'s Calibre, currently the most widely used solution.

Two user representatives at SNUG spoke of their experiences with IC Compiler. Neal Carney, VP of marketing at ARM Ltd, said his company achieved a 40 percent run-time gain compared with Physical Compiler and Astro, with comparable chip performance. In another example, he said, the run-time was comparable but chip performance was 8 percent better.

Don Friedberg, director of design methodologies at Agere Systems Inc., said his company had achieved 12 to 16 percent better performance, 10 percent better area and up to 40 percent run-time improvements compared with Physical Compiler and Astro. "These are dramatic results, and we don't really have to switch, since the same guys use PC [Physical Compiler] and Astro already," he said.

But Premal Buch, GM for Magma's design implementation business unit, said IC Compiler merely follows a strategy that Magma has already implemented.

"It appears that there's very little that's new, as much of what this announcement mentions, such as extended physical synthesis, Magma has already announced," Buch said.

"Synopsys is the last major EDA supplier to integrate its tools," said Eric Filseth, VP of product marketing for Cadence's IC digital business unit. "However, I don't think IC Compiler is what customers are looking for, especially given that Synopsys apparently intends to charge extra to integrate its own products."

IC Compiler, planned for production shipment in June, doesn't come cheap: A full technology subscription license for one year is $735,000.

Meanwhile, Synopsys will continue to improve, sell and support Physical Compiler and Astro for "quite some time," Domic said, although the company expects those products to "taper off" by the end of 2006.

- Richard Goering

EE Times




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