Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Interface

'Failsafe' clocking mechanism offers clock switchover

Posted: 30 Mar 2005 ?? ?Print Version ?Bookmark and Share

Keywords:micrel? sy89840u? sy89843u? lvds? cml?

Micrel Inc. is now promoting its SY89840U-SY89843U, and SY89837/8U family of ultra-low jitter LVDS, CML and lvpecl high-performance clock multiplexer ICs. The chips feature runt-pulse elimination (RPE) and Fail Safe Input (FSI) circuitry (which the company believes is unique and is trying to protect with a patent application).

The SY8984x MUX's clock switchover circuit guarantees no runt pulses (short cycles) when the inputs are switched from one clock to another (i.e., from the primary to secondary clock streams). Such a feature is important in data center and other mission-critical applications, in which a cough or short-cycle could result in false data triggers. While a number of manufacturers promote this form of clock switching, Micrel's architecture may be unique in that it does not rely on a phased-locked loop (PLL).

Optimized for precision clock switching architectures in enterprise server and non-SONET based networking systems, Micrel's clock multiplexers provide extremely low jitter, low costwhat Micrel calls a "precision alternative to PLL switching designs."

Another unique feature is an input stage that prevents unwanted oscillations and maintains output stability when an input signal's differential signal collapses or disappears. The MUX's input crosstalk isolation reduces crosstalk by up to 70 percent, the company claims.

AC performance for the devices guarantees clock frequency throughput from 1kHz to 1.5GHz, and rise and fall times of 250ps for LVDS and LVPECL outputs and 150ps for CML outputs. CML output options include internal source termination to reduce round-trip reflections and maintain low-jitter performance. Jitter performance is guaranteed to be less than 10psp-p, and within device, output-to-output skew is guaranteed to be less than 25ps. The product family guarantees operation over the full industrial temperature range (-40C to 85C) and supply voltage operation from 2.5V or 3.3V.

The 2:1 multiplexer family includes options with integrated fanout buffers. The SY89840U-SY89843U MUX series and SY89837/8 fanout buffers minimize jitter and simplify designs by integrating the termination required for differential outputs. This I/O buffer is designed to interface to any differential signal, AC- or DC-coupled, without any external components in the signal path.

The SY89837/8U LVDS fanout buffers, with RPE/FSI MUX inputs, are available in volume quantities. The SY89842U and SY89843U RPE/FSI multiplexers will be available in volume quantities by the end of April, 2005. Evaluation boards for all parts are also available. Pricing for the ICs start at $2.55 for 1,000-piece quantities.

- Stephan Ohr


Article Comments - 'Failsafe' clocking mechanism offers...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top