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Statistical tool shift: It's all in the timing

Posted: 01 Apr 2005 ?? ?Print Version ?Bookmark and Share

Keywords:statistical timing analyzer? signal integrity? sensitivity analysis? extreme da? correlation?

A design automation technologist, a professor and a venture capitalist have teamed up to promote what they say is a leap forward in chip design: a statistical timing analyzer. The founders of startup Extreme DA Corp. call their product a long-awaited enabling technology for 65nm and 45nm IC design.

The company now has a statistical timer and extractor in beta sites, and it is aiming for a production release by Q3. With Magma Design Automation Inc. and IBM Corp. also preparing technology in this area, however, it is too early to say who will be first to market with a production-quality commercial statistical timer.

What is clear is that statistical timing represents a turning point in chip design. While today's static timing tools consider best- and worst-case values, statistical tools provide statistical distributions of delays under varying voltage, temperature and process conditions. A statistical timing analyzer can tell a designer that a given clock speed will result in an 80 percent yield, allowing the designer to push performance as far as possible while staying within yield margins.

"If I close my eyes and open them five years from now, everything will be statistical," said Lucio Lanza, a veteran EDA venture capitalist and Extreme DA's chairman. "It's just a question of when it acquires commercial relevance."

Lanza and Larry Pileggi, professor of electrical engineering and computer science at Carnegie Mellon University, started talking about statistical timing analysis several years agoand looking for a team to implement it. The opportunity came when Mustafa Celik, who did post-doctoral work under Pileggi, left Magma Design in late 2003 to start a company.

"My idea was to do something in timing with an emphasis on signal integrity," Celik said. "Then I talked to Larry and he said, 'Why not add statistical timing, too?' He knew an investor who was really interested in this area, and I met Lucio, and here we are."

The first member of the technical development team was Celik himself. Now Extreme DA's CEO, Celik earlier developed extraction and signal-integrity engines for Monterey Design Systems and directed the timing and delay calculation group at Magma. The other developers are Kelvin Le, who devised a statistical timer at Carnegie Mellon; Yuji Kukimoto, a static timing-analysis expert; and Guy Maor, a software architect.

The Carnegie Mellon research was a starting point. "What CMU did was pretty good, but these guys took it as a seed and really rebuilt it," said Pileggi, who now serves as an adviser to Extreme DA.

The four developers set up shop in Lanza's office, where they remain to this day. "They were not distracted for anything," Lanza said. "Their job was developing. I told them, 'Don't leave that screen! Anything else, write it down and I'll take care of it.'"

Making an impact

Can four guys in borrowed office space make a big impact on chip design? Lanza, who as Artisan Components' chairman oversaw that company's sale to ARM for $1 billion, thinks he has another winner with Extreme DA. And Gary Smith, chief EDA analyst at Gartner Dataquest, likes what he sees.

"We pretty much know that statistical timing/power engines will be necessary at 65nm, more so at 45nm," Smith said. "Although I'm sure that if the big EDA vendors are working on them, we've seen no sign that they will be introduced in the near future. So that makes Extreme DA a significant announcement."

Extreme DA's stated mission is "variation-aware" IC analysis. "With new technology generations, process, temperature and voltage variations keep increasing," Celik said. He noted that this gives rise to varied corner cases, or combinations of factors such as voltage, temperature and oxide thickness, that require numerous individual runs with static timing analyzers.

A statistical analyzer can handle dozens of corner cases in a single run. Delays are correlated distributions, not single values. Spatial correlation, or distances between components, can be taken into account. When analysis is complete, a probability curve predicts yields for given clock frequencies.

Key to Extreme DA's timer, called XT, is a patent-pending "sensitivity analysis" capability. This lets designers evaluate yield sensitivity with respect to a given cell or gate, determining how a changed delay, or upsized or downsized cell, might affect yield. Celik said it is "about 10,000 times faster" than SPICE with a Monte Carlo analysis, although Extreme DA also supports that approach.

A variation-aware RC extractor that claims to be within 1 percent of 3D extraction accuracy is part of the package. "We believe you have to do it in the same tool," said Celik. Also part of the tool is a signal integrity capability, although it has yet to go into beta testing.

While previous papers have shown a performance overhead for statistical timing analysis, Celik claimed that XT runs faster than a single-corner analysis for a static timing tool while handling up to 128 corner cases. "Immediately, your signoff process will be about 100 times faster," he said.

XT is under evaluation at several large integrated device manufacturers (IDMs), including Toshiba America Inc. S. Krishnamoorthy, director of the advanced methodology group there, said that Toshiba is looking for a better way of evaluating how timing varies across a die, as well as a better understanding of how timing is impacted by process windows. While the evaluation is in its early stages, Krishnamoorthy said, the tool appears to use less memory and give faster turnaround time than static timing analysis.

One reason for working with IDMs, Celik acknowledged, is that they have foundry data needed by the timer. Extreme DA, he said, will "start to talk to foundries very soon" in hopes of gaining the process and yield information that fabless customers need. Meanwhile, he said, yield specialist PDF Solutions is running beta tests of Extreme DA's timer.

Lanza is not worried about competition from the big EDA vendors. "I think we're ahead by one to two years, and it will take three to five years for them to catch up," he said.

"A fresh start is actually pretty important," said Pileggi. "When you take existing tools and layer more and more on top of them, the results aren't good."

Still, competition is coming. Magma's Cobra development project includes statistical timing analysis and extraction.

Cadence Design Systems Inc. is also working on the technology, said Eric Filseth, VP of marketing for IC implementation at Cadence. Still, he said, "people are clearly going to do 65nm design without statistical timing analysis."

Synopsys Inc. has already introduced "multiscenario" analysis and on-chip variations into its PrimeTime static timing analyzer, said Rajiv Maheshwary, senior director of marketing for signoff and power products. Statistical timing analysis will target 65nm and 45nm designs, he said, and will "serve as the foundation technology for variation-based implementation and signoff."

But the one to watch may be IBM. The company has reported progress with its EinsStat statistical timer in recent conference papers.

Chandu Visweswariah at IBM's T.J. Watson Research Center said EinsStat now has an incremental capability and can handle non-Gaussian and nonlinear delay dependencies. He said the technology is in use inside IBM for ASIC design, but declined to comment on tapeouts.

The question now is whether IBM, which is not a commercial EDA vendor, will offer statistical timing to the outside world. "Access to this technology will be available, and evaluations are progressing as we speak," Visweswariah said.

- Richard Goering

EE Times




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