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Cobra strikes to reshape IC design flow

Posted: 01 Apr 2005 ?? ?Print Version ?Bookmark and Share

Keywords:nanometer ic design flow? yield optimization? silicon compiler? gate? asic?

Claiming breakthrough technology that will reshape the nanometer-IC design flow, Magma Design Automation Inc. is preparing to roll out its Cobra system. The company has restructured itself to focus on that technology, said Magma CEO Rajeev Madhavan.

Cobra promises to help automate the 65nm and 45nm design flow by tackling emerging problems such as yield optimization, on-chip variations and pervasive signal-integrity challenges. It includes integrated routing and optimization, a fast physical verification solution and what is claimed to be the first commercial solution for statistical timing analysis and extraction.

According to Madhavan, Cobra is a big step toward an elusive dreama "silicon compiler" that can automate the entire chip design process. "We have to automate the whole flow so that we not only solve 65nm and 45nm problems, but do it without increasing head counts," he said.

Cobra is the codename for a massive development effort that includes contributions from 11 acquired companies. Augmenting the technology developed at those companies, 125 Magma R&D employees worked on Cobra over an 18-month period, Madhavan said. He noted that Magma has "restructured the whole company" and created four business units to tackle the four areas addressed by Cobra: logic design, silicon design, signoff and analysis, and physical verification.

It is a big step for an upstart EDA vendor that, despite growing revenue, is still about one-eighth the size of either Synopsys or Cadence Design Systems. But it potentially places Magma in a much stronger competitive position against the two EDA giants.

Gary Smith, chief EDA analyst at Gartner Dataquest, said Cobra appears to be the first true 65nm and 45nm design system. "If this is real, it really puts Magma ahead with the whole connection to manufacturing," he said.

While the move from 130nm to 90nm has not resulted in a massive overhaul of EDA tools, the forthcoming shifts to 65nm and 45nm probably will, many observers say. Below 90nm, manufacturability becomes a far more nettlesome challenge. Yields become problematic, on-chip variations take on new significance and crosstalk can affect almost every net in the design. Also, designs could have 50Mgates or 100Mgates, threatening extremely long design cycles.

Cobra, Madhavan said, addresses all of those problems. And Magma has already gotten a start with the recent Blast Fusion 4.2 release, which adds a multithreaded router capable of supporting the "interconnect synthesis," or integrated routing and optimization, promised by Cobra.

Cobra rollouts will start first in the logic design area. Here, Magma promises technology that can map directly to standard cells, structured ASICs or fpgas, making it easy to move from one architecture to another. Also on tap are "physically aware" design-for-test and support for the synthesis and verification of timing constraints, including false and multicycle paths.

In the silicon design area, Cobra will provide routing that does on-the-fly optimizations for signal integrity, on-chip variations and power. With the new Blast Fusion router, Madhavan said, this added optimization won't appreciably slow the routing.

Combined routing and optimization is nothing new, said Eric Filseth, VP of product marketing at Cadence Design Systems. Indeed, he said, it is what Cadence's NanoRoute router is known for.

Cobra will also offer yield-based optimization, derived from work that Magma has done with PDF Solutions. Madhavan said it will ensure that cells or groups of cells are optimized for the best yields. While most Cobra components do not have product names yet, this one does: It will be called Blast Yield.

In the signoff and analysis area, Cobra will bring to life statistical timing analysis, long a topic in academia. While conventional, static timing analysis gives go/no-go results, a statistical analyzer provides a distribution curve showing what kinds of yields a designer can expect given varying parameters.

Madhavan said Magma has developed "unique algorithms" that reduce the overhead for statistical timing analysis to less than 8 percent. He also noted that the same product will provide statistical extraction, leveraging technology acquired along with Random Logic, and transistor-level timing analysis, leveraging technology acquired from Circuit Semantics.

The resulting timing signoff solution will attempt to crack the near-monopoly of Synopsys' PrimeTime product. Synopsys declined to comment on statistical timing analysis. Cadence, however, is working on the technology, Filseth said. "It's clear we can get through 65nm without having to go to a radically different timing architecture," he said.

The final area addressed by Cobra is physical verification, and here Magma has used technology acquired from Mojave Design to build what it claims is the fastest design-rule-checking (DRC) and layout-vs.-schematic (LVS) tool available. Madhavan said the tool can process a 20Mgate-design in three and a half hours, and the goal is to reduce that to two hours.

While other DRC/LVS tools compare edges, Madhavan said, Mojave developed a "shape-based" engine that uses algebraic formulations. "It's completely scalable and can be distributed to any number of processors linearly," he said.

The Cobra DRC/LVS tool takes dead aim at Mentor Graphics' Calibre product, which is the current market leader.

Mentor is confident that it can retain that lead; the company continues "to invest heavily in order to maintain our leading-edge technology," said Joe Sawicki, general manager of Mentor's design-to-silicon division.

- Richard Goering

EE Times




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