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Designing for yield heats up

Posted: 01 Apr 2005 ?? ?Print Version ?Bookmark and Share

Keywords:design for yield? foundry? library? asic? fpga?

Two library announcements!one by a foundry and one by an independent library vendor!are signaling a sea change in how the chip industry thinks about the critical issue of design-for-yield (dfy).

From a talking point in academic papers and a carefully hidden issue in leading-edge foundry engagements, DFY is now on the threshold of becoming a competitive weapon in the open market. This transition is bringing into focus the differing interests of EDA vendors, intellectual-property vendors and foundries.

Richard Tobias, VP of the ASIC and foundry business unit at Toshiba America Electronic Components, summarized the issue in a DesignCon panel. "It used to be that as a factory ran more wafers on a new process, they got better at it," Tobias said. "After a while they would be good at the process and everyone would get good yields. But now, even after the factory is good at a process node, the chip design makes a big difference in the yield."

This shift of responsibility for yield has had dramatic!if predictable!results. Initially, it sent everyone!from design teams to EDA vendors to foundries!scurrying for cover.

But as it became clear that the problem could obstruct migration to 90nm, a sense of shared responsibility developed. Customers formed what amounted to joint development relationships with their foundries to attack yield issues. Altera Corp.'s VP of technology, Francois Gregoire, said his organization had more than 100 engineers working with their foundry to co-develop a 90nm FPGA line and the process on which it would be fabricated. And Vincent Tong, Xilinx Inc.'s product technology division VP, described a relationship with Toshiba in which the chip team took calculated risks in initial design, then a second engineering team tuned for yield, all in concert with Toshiba's process integration experts.

Foundries, ip vendors and EDA companies are now rushing to market products or features aimed at the yield problem.

In principle, the simplest approach is to construct a design rule file that forbids structures that threaten yields. But early on, engineers were unable to identify mechanisms for design-dependent yield loss. So they could not devise adequate rules. As a result, sources say, designs slipped into a pattern: Follow the rules, get crummy yields. Consult with the foundry, revise some parts of the physical design. Get better crummy yields. Repeat as needed until the word "crummy" drops out.

"Most 90nm foundries have now developed good, prioritized design rules," Jim Jordan, VP of marketing and business development at BindKey Technologies, said. "Designers can expect a 4-6 percent improvement in yield by following all the rules, compared to not following them all."

For some design teams, the risks of breaking the rules weigh heavier than the costs of complying. For these teams, library vendors are developing special libraries that conservatively interpret the rules file. Since exact interpretation is helped by exact knowledge of the process!information that foundries have proved utterly unwilling to share with most customers!this gives the foundries themselves a competitive edge in the library market.

tsmc has jumped on this advantage by offering!free through its library partners!a TSMC-branded set of 90nm libraries. "We have always developed our own libraries for process integration uses and as a means of working with third-party library vendors and EDA companies," a spokesman for TSMC North America said.

That puts competitive pressure on the third-party library vendors who now must distribute a free set of libraries that, while process-specific, compete against their own base libraries. Virage Logic Corp., for one, is replying with a more-nuanced DFY approach of its own.

Virage President and CEO Adam Kablanian argues that the approach to DFY at the library level should depend not just on the process node, but on what yield issues that particular process is having at the time. As 90nm processes are maturing, he said, some of the very large sigmas that were seen initially are shrinking. Hence, a chip that was designed for good yields with early process data might be unnecessarily conservative now, leaving density or performance on the table.

"Different yield issues are important at different stages of the process evolution," Kablanian said. So Virage Logic has introduced a family of DFY libraries, with cell sets addressing particular yield problems. "There are four variants addressing different kinds of problems," he said.

Integrating the solution

But in the long run, DFY cannot be thought of as just a library choice or post-layout inspection step. "This work must be pushed up as far as possible into the design flow, not tacked on as an afterthought," warned Marc Levitt, VP of the design-for-manufacturing business unit at Cadence Design Systems Inc. Levitt telegraphed the next big battle in advanced chip design flows: integrated DFY.

Even this is not enough in the eyes of some. Some EDA vendors have suggested that the real solution is to make yield take its place as just another design characteristic. In this scenario, whole blocks of hard IP would be characterized for yield.

This implies that someone, whether foundries or independent vendors like PDF Solutions, must move from design rules to models that predict yield for individual structures.

The models would then be incorporated into the synthesis and layout tools in the design flow. "The purpose is to give the average fabless semiconductor team the same chance that the huge integrated device manufacturers have of getting good yields," Virage's Kablanian said. For 90nm production to take its place on the Moore's Law curve, that has to happen.

- Ron Wilson

EE Times




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