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China beating U.S. in verification?

Posted: 01 Apr 2005 ?? ?Print Version ?Bookmark and Share

Keywords:verification? systemc? ansi c? ip? china?

There is an old expression that says the grass is always greener on the other side. This is a feeling that has existed for a long time between the hardware and software communities.

Software engineers look at how much effort the hardware guys put into their functional verification, resulting in much lower bug rates. Hardware engineers, while noting the buggy nature of software, have started to emulate software engineers by migrating design languages to look more and more like software, introducing new languages such as SystemC or using ANSI C itself.

Looking at the figures, the hardware community may already be experiencing some of the problems associated with this change. Hardware bug rates are up and more chips are failing, despite the fact that over 50 percent of the total time is devoted to verification. Some companies have even reported spending 80 percent of their time on verification.

Part of the reason for this shift in time allocation is the success of reuse. With more of a design being reused from previous designs or additional IP being brought in from third parties, there is less time that needs to be spent on the new logic that will differentiate this chip from the commodity market. However, reuse has not yet reached the point of maturity where the industry has reuse without the need to re-verify.

As the size of the design grows, the verification challenge also grows. New techniques such as assertions, pseudo-random generation and coverage of all different types have been introduced, and while they help, they have not slowed down those alarming verification trends. So what is the root cause of the problem? I think it inertia.

If we look at the basic methodology in place for verification, it is based on a bottom-up process. First to be verified are the smallest blocks, perhaps the output from a single engineer. These verified blocks are then integrated together into larger blocks which are then verified, and are combined into still larger blocks.

The process continues until the whole system has been assembled, and then we check to see if it actually does something useful. In this last stage, what is actually being verified is that the system works as intended in the specification. In other words, the specification is being validated. This is a little late in the process to find out if the specification was wrong!

The reason this methodology is used is based on history. Back in the late 1970s, manufacturing test was used for board-based systems. The chips or components for a board were tested when they were received. The bare boards were tested, and then retested after they had been loaded with the components.

The boards were placed in a rack and the system tested. This process was put in place by the tester companies, and it was these companies who created the first generation of software verification tools. They were "virtual testers" so that tests could be developed without consuming valuable time on the expensive hardware.

However, there is a big difference between these two flows. With the board test process, it is known ahead of time that the chips perform the desired function. In other words, the chips are validated ahead of time and then verified that they perform to specification when used.

This is not the case with the development of a chip. When a module is verified, it is not known if the verified function actually performs the necessary function in the system. Simply, we verify before we validate. I believe that this is the root cause of the verification problems of today.

China does not have this inertia built into its system, nor does it suffer from its engineers appearing incompetent if they wish to rely on tools. This gives it a huge opportunity to move ahead in the area of functional verification. If successful, China could produce chips much faster and of better quality than the rest of the developed world.

To do this, it is necessary to build a top-down verification environment, where the specification is validated first. As partitions are made into hardware or software components, they should be verified in the context of the specification. Finally, when the specification for a block has been isolated, it will be known that it is the function needed by the system, and the engineer can construct it knowing that if it is implemented correctly, then the system will function correctly.

Emerging electronic system level tools are moving closer to this paradigm, but if China takes this up as a priority, then it could make the grass on the other side turn brown. It is not necessary for a developing technology nation to replicate the problems of the established world, and if successful, it will still take a long time before the inertia of the current engineers is pushed aside.

Brian Bailey is an independent consultant helping companies improve their verification efficiency.

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