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EDA/IP??

Tool can cut design cycles by 80%

Posted: 01 Apr 2005 ?? ?Print Version ?Bookmark and Share

Keywords:analog devices? adi? pll circuit design? evaluation tool? adisimpll?

Analog Devices Inc. (ADI) said that its latest version of its PLL circuit design and evaluation tool helps designers cut design cycles by up to 80 percent.

The ADIsimPLL v2.7 features enhanced synthesis and simulation capabilities, expanded libraries and Web access, streamlining the RF development process for users of ADI's fractional-N and integrated VCO/PLL products.

ADI's fractional-N and integrated VCO/PLL products are used in wireless base stations, LAN, mobile handsets/PDAs, broadband wireless access, industrial and instrumentation and test equipment, satellite, sonar and CATV applications.

ADIsimPLL v2.7 supports simulations of all key non-linear effects that impact PLL performance. It also adds loop filter options, allowing designers to optimize the synthesis algorithms and lower the loop filter's contribution to the overall PLL phase noise.

"When we first introduced the ADIsimPLL tool two years ago, it redefined PLL synthesizer design by removing time-consuming iterations from the design process, increasing accuracy and speeding designs to market," said Christian Kermarrec, VP, RF and wireless systems, ADI. "Now with the enhancements features in v2.7, design cycles can be cut by up to 80 percent when compared with traditional evaluation methods."

ADIsimPL v2.7 allows designers to modify derived parameters such as the loop bandwidth, phase margin and pole locations and immediately observe the effects of the change on performance.

The new tool is available now free of charge as a download, allowing designers to run simulations locally.

- Ismini Scouras

eeProductCenter




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