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EDA/IP??

Prover equivalence checker supports Actel design flows

Posted: 04 Apr 2005 ?? ?Print Version ?Bookmark and Share

Keywords:echeck? equivalence checker? design verification? fpga?

Prover Technology Inc.'s eCheck equivalence checker has been validated for design verification in Actel Corp.'s Libero integrated design environment (IDE). Prover has also joined Actel's alliance program. Prover eCheck provides designers with an automated solution to identify implementation inconsistencies for Actel's antifuse- and flash-based field-programmable gate array (FPGA) devices.

By using formal verification techniques, the Prover eCheck exhaustively verifies synthesis and place-and-route faster and with a much higher degree of automation than simulation-based verification solutions.

Actel's Alliance Program is committed to providing integrated solutions that work with existing EDA software and design flows. Actel works closely with its EDA partners through the Actel Alliance Program to provide early technical information on new Actel releases so the EDA partners can offer timely support.





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