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Infineon claims major power efficiency for ADSL2+ chipset

Posted: 04 Apr 2005 ?? ?Print Version ?Bookmark and Share

Keywords:infineon technologies? infineon? adsl2+? chipset? dslam?

Infineon Technologies AG has introduced an ADSL2+ chipset targeted at DSLAMs and digital loop carriers that incorporate Class D line drivers which are said to make the part the most tightly integrated and power efficient in its class.

The company says OEMs can build a 16-channel ADSL2+ system with just 5 chips when using the device, dubbed the GEMINAX PRO.

Christian Wolff, VP of the company's communications business group and GM of the wireline access operation, also revealed that Infineon would 'very, very soon' outline details on its first parts conforming to the emerging VDSL-2 standard. He termed the very high speed DSL technology "the universal and ultimate DSL standard."

The International Telecommunications Union (ITU) is due in May to formalize the standard, which will use a unified modulation scheme based on discrete multitone technology and is aimed at relatively short loop, 100Mbps symmetric transmission in both downstream and upstream.

VDSL-2 consumes as much as 30MHz of bandwidth compared to about 2.2MHz for ADSL2+, and 12MHz for the existing VDSL.

Talking at the introduction last week (March 31) of the latest additions to the GEMINAX range for ADSL2+, Wolff also said the market for DSL chips has had a tough 2004, "and this difficult situation is likely to lead to further consolidation."

Wolff suggested that of the six significant players in broadband silicon, down form 9 three years ago, "only two are showing any growth, specially us (Infineon), while the other 4 are losing market share, and I would not be surprised if by 2008, there were only two to three major players left. And our recent significant increase in market share for CO DSL, form about 4 percent in the fourth quarter of 2003 to 16 percent a year later, according to figures from the Dell'Oro market research group, indicates that we will be in good position to be one of the survivors."

Other companies involved include Conexant, Texas Instruments, Broadcom, ST Microelectronics, Ikanos Communications, Analog Devices and Metalink Ltd.

Wolff said a GEMINAX PRO chipset, comprising a 16-channel ADSL2+ Digital Front End (DFE) and a 4-channel Analog Front End (AFE), with integrated low-power Class D line drivers, reduces power dissipation, footprint and overall system costs by up to 30 percent, in comparison to other chipsets currently available.

The company maintains high power dissipation of currently available ADSL2+ line drivers limits the integration to two channels per device. Instead, by deploying switched-mode (Class D) line driver technology, the power dissipation of the line driver is reduced by 50 percent to less than 350mW per channel, allowing the integration of four line drivers and AFE channels into a single device.

"From a standards point of view, ADSL2+ is solved and we are seeing deployments in a number of areas, specially Asia and Europe. But cost remains a big issue for our customers, the DSLAM makers, and their customers, the operators, so anything that helps bring costs down at the system level helps. And our latest devices certainly do that by significantly reducing the number of external components, improving the density of the boards for the line cards, and on power dissipation," said Wolff.

The GEMINAX PRO range consists of a 16-channel ADSL2+ Digital Front End, the GEMINAX-D16 PRO, and a 4-channel Analog Front End with 4 integrated low-power Class D line drivers, dubbed GEMINAX-AL4 PRO.

The low power consumption, decreased chip count as well as per-channel footprint of only 500mm? means capacity per line card and shelf using the chipset can be significantly increased.

The parts support ADSL full-rate (G.992.1), ADSL-lite (G.992.2), ADSL2 (G.992.3), ADSL2-lite (G.992.4) and ADSL2+ (G.992.5) standards.

The D16 PRO version comes in a 23-by-23mm PG-LBGA-484 package, while the GEMINAX-AL4 comes in a 13-by-17mm PG-BGA-192 package. Samples will be available in May, and volume production is planned for 3Q 2005. Sample quantities of the chipset cost $6 per line.

- John Walko

EE Times




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