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Crolles2 partners extend joint R&D to include sharing of SoC IP blocks

Posted: 13 Apr 2005 ?? ?Print Version ?Bookmark and Share

Keywords:soc? ip blocks?

Crolles2 Alliance partners STMicroelectronics, Philips Semiconductor and Freescale Semiconductor are planning to extend the R&D program to include the creation and validation of high-level system-on-chip (SoC) intellectual property (IP) blocks.

The companies say implementation and completion of an agreement is still subject to the successful conclusion of a contract between the partners. However, if it goes ahead, as they clearly believe it will, the companies stress this would be the first time in the industry that a group of major semiconductor companies has agreed to share proprietary SoC IP blocks.

The Crolles2 alliance is a huge European R&D effort aimed at the industrialization of CMOS process technologies. The companies say bundling of effort in generation, validation and support of high-level SoC IP blocks is a logical next step in the work already under way.

The goal is to shorten the time-to-market for increasingly complex chips.

The three chip companies plan to set up the Library and IP Partnership (LIPP) with operations across a number of sites, which includes Grenoble, France, Eindhoven, The Netherlands, Austin, Texas and Bangalore and Noida in India. Headquarters would be Eindhoven.

The partners already share a common set of design rules and foundation library sets as part of the joint technology developments. The preliminary understanding is to extend this alignment to include their SoC IP blocks and re-use methodology.

LIPP would provide and support re-usable SoC IP blocks that the partners plan to use in their SoC designs at 65nm node and beyond.

The first projects undertaken would be the development of re-usable IP blocks for advanced I/O interface standards, common analog IP blocks, embedded processors and SoC infrastructure IP for the Alliance's 65nm CMOS process.

- John Walko

EE Times





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