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Tower Semi debuts 0.18- and 0.13-?m libraries

Posted: 15 Apr 2005 ?? ?Print Version ?Bookmark and Share

Keywords:tower semiconductor? design library? standard cell? i/o? memory compiler?

Pure-play independent specialty foundry Tower Semiconductor Ltd announced this week (April 13) the introduction of its in-house set of 0.18?m and 0.13?m design libraries.

The company's standard cells, I/Os and memory compilers, for use in complex system-on-chip (soc) designs, are based on Synopsys' library technology, and are available to Tower customers at no charge.

Tower's 0.13?m libraries will augment the existing 0.18?m libraries, which were proven on silicon and have been used in multiple high-volume customer designs. Tower libraries include a comprehensive set of views for leading EDA tools.

"In line with our specialized foundry strategy, Tower customers can now enjoy flexible, in-house customization to meet specific customer and technology segment needs," said Rafi Nave, VP of customer services, Tower Semiconductor, in a statement. "Our customers can now benefit from high-quality, low-risk solutions, resulting in faster time-to-market and faster time-to-production in the most affordable way."

The standard cells have been optimized for high place-and-route density. A wide range of input/outputs with over-voltage input tolerance, noise-quieting circuitry and ESD protection are available in both in-line and staggered configuration. Memory compilers for ROM, high-density SRAM and dual-port RAM provide high performance, high density and configuration flexibility.

- Spencer Chin

EE Times

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