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DATE minds offer an array of fixes for SoC design

Posted: 18 Apr 2005 ?? ?Print Version ?Bookmark and Share

Keywords:design automation and test in europe? samsung electronics? soc?

The challenges of designing high-volume, high-performance systems-on-chip may jeopardize their success unless there is a breakthrough from system-level design through manufacturing, according to the keynoter at last week's Design Automation and Test in Europe conference here. That speaker and others agreed that such milestones are unlikely to be marked without tighter industry collaboration.

Jeong-Taek Kong, VP of computer-aided engineering at the Semiconductor Business Unit of Samsung Electronics Co. Ltd., said in his keynote here that SoCs can enable products that comply with rapidly changing market requirements. But today's leading-edge semiconductor fabrication processes considerably reduce process yield and hence lengthen the SoC production ramp, affecting profitability. "Other methods must be developed and must be the result of industry collaboration," Kong said.

Yervant Zorian agreed, saying, "The days of independent system design, chip design and manufacturing are over." The chief scientist at Virage Logic Corp., he said, "Chip design is increasingly impacting the cost of manufacturing, and manufacturing's error rate, mask costs and process technologies increasingly impact design methodology." Likewise, Zorian said, both chip design and manufacturing affect which systems get to market.

The answer lies in cohesive design, suggested Garry Hughes, vice president of ASIC and foundry solutions at IBM Corp.'s Systems and Technology Group. Hughes said designers should use timing statistical analysis and noise analysis, integrate the circuit-timing environment into the design flow, incorporate test in a correct-by-construction methodology and plan up front for both chip and package design.

"All of these functional methodologies need to be integrated into one cohesive design flow. Having the best pieces of a technology is not good enough; you need to collaborate with others for the good of the many," he said.

Design-for-manufacturability in 90-nm applications and below can dramatically affect the business performance of chip manufacturers. It can also significantly affect age-old chip design flows. DFM techniques in modern design flows are lacking because "VCs [venture capital firms] support point tools and not the formation of DFM-based industry," said Rajeev Madhavan, chairman and chief executive officer of Magma Design Automation Inc. He called for next-generation physical verification tools to "process zillions of polygons in a short period of time."

The focus is on predictable, high-quality design results despite the challenges associated with these next-generation technologies, said IBM's Hughes. "This scenario is complicated even further by the need to address these challenges across a wide spectrum of products, ranging from high-frequency processor designs to extremely complex ASIC designs." Hughes said that in the nanometer era, the common factor for ensuring market leadership across this broad variety of products is achieving single-pass design success to avoid costly respins and the loss of market opportunities: design turnaround time must be minimized without compromising design efficiency and first-time-right requirements.

Hughes said that design automation tools must balance both requirements, while giving designers information that enables them to "design around" potential trouble spots in both today's and tomorrow's environment to ensure an exceptional level of built-in quality.

Raising quality through better design yield methodologies is one way. Walden Rhines, chairman and chief executive officer of Mentor Graphics Corp., cited a couple of instances where yield methodologies were used to improve results. In one, two wafers had the same design, but elements on the first wafer switched at speeds that were different from those on the second wafer. Compensating for this skew resolved the issue for the wafer run. Rhines called for "process guys to share accurate process recipes and to develop a taxonomy of terms "we can all understand and use."

"We need to establish a collaborative partnership model," said Kees den Otter, president of TSMC Europe. He called for a platform technology approach that would be tied to libraries and IP, the back-end process, EDA and design process.

- Nicolas Mokhoff

EE Times




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